In 2012, the CAN with Flexible Data rate had been presented at CiA's international CAN conference. In the meantime CAN FD has been internationally standardized, the semiconductor manufacturers have developed CAN FD hardware, and the car manufacturers currently put CAN FD into service. In 2019, we can see first production cars, whose embedded control networks make use CAN FD. As CAN FD supporting microcontrollers became available that are suitable for small applications, such as e.g. sensors, everything is prepared to pave CAN FD the road to the non-automotive market, as well. Classic CAN and CAN FD are not interoperable. But especially long-lasting applications need to consider solutions, to run old CAN-based devices and new CAN FD-based devices in parallel, to avoid an expensive exchange of the entire embedded control network. The presentation presents solutions to migrate from CAN to CAN FD smoothly, thanks to the scalability of CAN and higher-layer protocols like CANopen or J1939.

Securing existing industrial communication protocols like Controller Area Network - CAN (FD) - requires a look at all protocol layers. Although security solutions are known for most individual layers, there are practical limits to their application such as resource constraints. Our paper examines how existing security solutions for individual layers can be combined to best complement each other in a real-world CAN/CANopen system. The discussed security mechanisms are: • black- and white-list filtering of CAN (FD) frames, transfer rates limitation and secure configuration • secure grouping and authentication with CANcrypt • end-to-end security protocols like TLS to typically secure remote end-to-end security, e.g. for diagnostics We look at the entire lifecycle of a system, also adding/removing devices, key distribution and diagnostics and service. We show how with a smart combination of security mechanisms they can complement each other and significantly improve overall system security.

Since the CAN in Automation (CiA) has published the CiA 1301 – CANopen FD in September 2017, one CiA technical group discusses how CANopen Layer Setting Services (LSS) should be adapted to CANopen FD. LSS Fastscan service used in the CANopen for identifying unconfigured LSS slaves is complex and requires up to 128 messages exchanged. Benefited from the larger payload of the CANopen FD, the full 128-bit LSS address is used in the new service – LSS switch state selective FD service. The 128 bit LSS address is divided into 32 Nibbles of 4 bits. With each LSS master request, devices verify if their own LSS address matches the request and if it does, they respond with the messages matching their own next Nibble. The complete LSS address can be identified with exchange of only maximum 33 messages. The audiences will learn the operating principles, the service and protocol specification, and the operation sequences, as how to identify LSS slave if LSS address is known or unknow.

• In the IoT, many sensors & actuators may not yet be addressed directly via Internet Protocol (IP) • Single Pair Ethernet (T1, “SPE“), already successful in the automotive industry, allows for a new perspective • Advantages of a seamless IP-based communication layer from sensor to cloud • Simplified infrastructure for the connection of sensors & actuators in comparison to legacy solutions • TCOP: Plug & Play capabilities of intelligent terminals = reduced integration efforts • Local data processing & storage of meta information • Hardware-based end2end encryption using standard protocols • Enhanced data sovereignty for new, data-driven business models (cloud applications) • SPE market overview: existing & planned standards for different use cases • Differences to the “classic” Ethernet • Reduction of component-size and comparison to other intelligent sensor systems (e.g. IO Link) • Economic development of new industrial areas of application with T1 • Use Case: SPE-based smart building retrofit

Beginning in the automotive industry, Single Pair Ethernet (SPE) is about to enter the wider industrial market. With this change, filter design needs to adapt. Outside the automotive, the SPE isolation requirement according to IEC62368 is 1500V/60s. The commonly used 50V isolation caps cannot fulfil this requirement. Instead of using large and expensive isolation caps, Würth Elektronik recommends signal transformers specially designed for high bandwidths. With additional Common Mode Chokes, TVS diodes and caps, a full filter solution, capable for a stable signal transfer up to 600 MHz (1000 Base-T1) can be realized. The presentation shows examples and detailed measurements for the filter design from connector to PHY chip to fulfil all necessary EMI and safety requirements according to IEEE 802.3bw (100 Base-T1) and IEEE802.3bp (1000 Base-T1). Additionally, information about further Single Pair Ethernet development activities inside Würth Elektronik eiSos will be divulged.

This presentation provides an example of the mixed-critical ROS2 stack implementation based on VxWorks RTOS, embedded Linux, and hypervisor from Wind River. Turtlebot3 was selected as a robotic demo platform controlled by the SBC (single board computer) that runs a Hypervisor with several guest OS instances. We demonstrate a hardware agnostic approach by utilizing two different SBC HW platforms: Xilinx-based ARM board and Intel UP2 board. The hypervisor provides a separation of safety from non-safety and real-time from best-effort applications and allows us to build a mixed-critical system using multicore SBCs. One of the guest OSes is VxWorks - very few solutions available on the market which is already fulfilling safety and real-time requirements. ROS2 dashing release and turtlebot3 ROS2 middleware were ported to the VxWorks. On top, we run a collision-avoidance ROS2 application. Embedded Linux partition serves as a communication gateway to the external world and provides an example of a non-critical software stack. We demonstrate that if the non-critical guest OS fails and gets rebooted the safety-critical part still runs and performs its control functions.

Most people consider the OS design like a completed piece of work, and concentrate on higher software layers in their system. This could not be further from the truth: research is still strong on operating system design, and increased software concurrency and parallelism, as well as safety and security concerns are pushing towards new designs. While it is mostly approved that a microkernel design leads to a more robust system, scaling up the number of cores and running a single OS over a distributed platform remains a critical step for next-generation computing. This presentation focuses on the more recent design in the Operating System field, the multi-kernel approach. It will first cover the history of using monolithic design, then microkernel to improve separation memory-wise, and the evolution towards a multi-kernel design for separate CPU management. Some performance concerns and results will also be discussed.

Real-time Operating Systems are quickly becoming a must have component in embedded applications but industry best practices are far and few between. In this session, we will examine how to decompose an application into tasks, set proper thread priorities and manage data flow through application. We will also cover general best practices for efficient design.

Building higher-order multi-threaded communication mechanisms in C Communication between tasks is a critical aspect of concurrent design. Getting your communication patterns wrong can lead to incorrect or unpredictable system behaviour, corrupt system state or performance issues. Starting from well-known patterns for mutual exclusion, signalling and data-sharing we'll build mechanisms for we'll explore some higher order patterns of task communication. These patterns abstract the process of inter-task communication, making it more consistent, it robust, easier to test and easier to document. No particular RTOS is targeted in this session; we'll use an independent OS abstraction layer. The aim of this is to allow attendees to implement these patterns on their own RTOS, or as part of their own OS abstraction layer.

The difference between a semaphore and a mutex is often misunderstood. This topic is the source of one of our most popular and enduring Blog posts, which is why we have suggested it for Embedded World. In this tutorial, we will: • Provide a clear understanding of the difference between the binary semaphore and the counting semaphore. • Explain the inherent dangers associated with using the semaphore. • Highlight the history of the binary and counting semaphore and some of the associated problem areas • Identify how a different RTOS construct, the mutex, may overcome some, if not all, of these weaknesses • Cover mutual exclusion problems and how to address them for both circular deadlock and non-cooperation

AUTOSAR standards have always been weighty documents. But compliance with AUTOSAR’s specifications does not necessarily imply compliance with related standards and guidelines such as ISO 26262 (functional safety) or SAE J3061 (cybersecurity), which in turn require the use of coding standards - perhaps those promoted by MISRA or CERT. Each of these documents is very well intentioned but it can be very difficult to keep track of all of their requirements concurrently, let alone be sure that they have been complied with. This paper will outline a methodology designed to ease this challenging development. It will explain how functional safety and cybersecurity related objectives are complementary and can be met in tandem, as can the coding standards they each champion. And it will outline how automation can help keep track of compliance with the whole standards stack irrespective of functional requirement changes that are so familiar to many, despite the rigors of the ISO 26262 V model.

During more than 20 years of experience in the certification of safety related systems (HW/SW) according to safety standards like IEC 61508, ISO 13849 and ISO 26262 we have seen recurring issues due to misunderstanding of safety related key concepts. We have already presented a first selection of issues at Embedded World in 2018. Now we have extended our collection and will present the outcoming. Sharing this experience can help persons working active in Functional Safety Projects to avoid typical pitfalls and setbacks.

IEC 61508 is the Series of Standards that defines the use of Safety Functions within Industrial Applications to reach certain Levels of Risk Reduction known as Safety Integrity Levels SIL. The Need to update this Series of International Standards was identified by many nationally responsible Entities, leading to the Start of National and International Efforts to work on certain identified Topics. For Germany, members of the DKE Committee GAK 914.0.3 support the Updates related to Safety Software. This Presentation gives an Overview of the treated Topics and an Outline of discussed Proposals.

Currently IEC 61508 is going through its second maintenance process (IEC SC 65A MT 61508-1/-2). As IEC 61508 is a Basic Safety Publication, changes in this standard will have an impact on application specific standards and the development of new products. This presentation gives a short overview of the planned modifications and highlights the most important parts for the user and their possible impact on current and future developments. The third edition of IEC 61508 will update the requirements for the development and selection of complex semiconductors, will improve the topic of common cause failures and specify how to treat the failing of diagnostics. The requirements on tool classification and qualification will be extended. What does that mean for your current development? You might need to do a better tool classification and qualification, common cause failures need to be analyzed more systematically and you might need to reconsider your selection of semiconductors. How much credit can you take from semiconductors with integrated diagnostics? The answers to these and other questions will be given.

IEC 62443 is a global standard designed to help reduce the risks associated with the exposure of Industrial Control System (ICS) networks to cyberthreats. IEC 62443-4-1:2018 describes a cybersecurity focused process for the development of individual components for use on an ICS network. It details principles to be applied to each development phase - from security requirements definition, through verification and validation, and on to support processes for the product in the field. This paper will address the concerns of ICS product developers who currently work to established development processes structured to conform with the functional safety standard IEC 61508. It will argue that IEC 62443-4-1:2018 provides an opportunity for development teams to apply a proactive approach to cybersecurity that complements the needs of functional safety standards. And it will assess how the need to comply with the two standards in parallel might impact the administrative burden of the project.

One of the most common persistent memory technology in today's embedded systems is NAND flash memory. Raw NAND flash, as well as eMMC chips, have a limited number of write/erase cycles. To get a long lifetime several strategies are used such as garbage collection, wear-levelling and error correction code algorithms. Potentially going through low-level firmware on the eMMC controller and across several layers of system software, it is rather difficult for an application programmer to understand what particular wear his program may impose on the underlying NAND flash. We are discussing an implementation to monitor the flash usage on the block level which can be used to make more accurate lifetime estimations and provide feedback to an application program for storage-related optimisations.

Quality of an embedded memory system is inherently dependent upon the capability of a memory device to retain existing data and its ability to continue to record new data. Managed NAND memory products must therefore be selected with Data Reliability in mind. Traditionally, however, selection of embedded memory products is limited to restrictive and ambiguous parameters which often result in lost value-added opportunities. By anticipating managed NAND capabilities and advantageous operations, manufacturers can improve product quality, reduce manufacturing costs, and solidify their relationships with their customers. This session focuses on in-depth instruction-set for managed NAND Data Reliability characteristics and methods as well as how designers can increase the security and quality of their products through simple strategies for considering memory selection.

Flash media is fabulous for most use cases, but heavy reads can cause correctable errors. Linux flash file systems actually shorten the life of the media when dealing with these errors. How does this change with multiple bits per cell, including recent QLC NAND? This paper will cover both this problem and the impacts in detail, from flash file systems to SSDs and other NAND flash-based media.

Memory architecture in autonomous vehicles, both volatile (DRAM) and non-volatile (Flash) memory, is one of the main performance bottlenecks of such embedded systems. This paper describes the key subsystems that demand exceptional performance from memory. AI based sensor fusion for autonomous L5 demands up to 1TB/s of bandwidth from the volatile memory. Sensors and video recording black box, that may help to determine the root cause of an accident and become mandatory in various countries, demands very high endurance from the non-volatile memory. New solutions and memory architectures that enable such performance are discussed in this paper, as well as centralized and distributed system architectures and the associated demands from memory in each case.

Advanced node process technology (<40nm) will be the workhorse for the next decade of automotive, Industrial and multi-market solutions. These advance foundry processes will enable the move to autonomous driving, better health care through mobile pervasive monitoring, more efficient and greener industrial processes and machine learning. Embedded non-volatile memory is a key requirement for each of these applications. The speaker will give a perspective on the current state of embedded eNVM offerings at 28nm and below and will share proof points to demonstrate that MRAM technology at 22nm is the robust and timely choice for customers which to develop differentiated products now for these classes of application

Although not designed for embedded software development, C is the most popular programming language for such application. We will consider why the language is so popular and conduct a brief “refresher” of C language functionality, with an emphasis on the benefits to the embedded developer.

Why RUST won’t replace C (just yet anyway) The RUST programming language is one of the ‘new kids on the block’ – so what does it offer to the C and Modern C++ embedded development community? In this presentation, Niall Cooling will discuss: • Outline of the RUST language; its main uses and features from an embedded development perspective • Challenges and opportunities when using RUST in an established industrial environment • Can RUST and C co-exist? • Conclusion

The choice of the programming language is a fundamental decision to be made when defining a safety-oriented software development process. It has significant impact on code quality and performance, but also on the achievable level of safety, the development and verification effort, and on the cost of tool qualification. Traditionally, safety-critical systems have been programmed in C or ADA. In recent years, also C++ has entered into the discussion. C++ enables intuitive programming, but its inherent language complexity is much higher compared to C. This has implications for testability, code coverage, performance, and code analysis. Further issues to be considered are tool chain diversity, the role of the standard library, and tool qualification for compilers, analyzers and other development tools. The talk summarizes the requirements of different safety norms, illustrates development and verification challenges, and discusses tool qualification.

Acting as an introduction to the MISRA Stream, this presentation will discuss the current status of the MISRA C, MISRA C++ and MISRA Autocode guidance, together with current and future developments. In particular, it will talk about AutoSAR C++ and MISRA Compliance, as well as forthcoming updates to the main MISRA guidelines.

New MISRA C++ programming guidelines are on their way and several experts from the ISO C++ standardization committee are participating in its development. This guarantees that the upcoming guidelines will address current C++ best practices. Those practices allow to express more software with less code that is often also more efficient and safer than current industry practices in the embedded software world. This talk is a call to action to educate your developers to be able to write MISRA C++ conformant code in the near future. It will give examples of how future MISRA C++ 202x compliant code will look like and provide an overview, what obsoleted practices your developers might have to unlearn and what new modern C++ quality practices need to be mastered. "If you think education is expensive, try ignorance" (attributed to Derek Bok, Ann Landers and others).

Following the success of Voice Assistant over Smart Speaker, a new breed of voice-enable devices are services are being development which will enable massive dissemination of voice activation services, everywhere. Smart home, smart health and Industrial applications are some of the first that will benefit with deployment through smart home appliances, health assistants and smart manufacturing. This talk goes through the use case study of a constrained IoT voice assistant implementation on an single chip ultra low power, lost cost device. It describes the HW and SW functional blocks that is needed in order to perform voice recognition in harsh audio environments. It shows the benchmarks of analog front end processing and Key Word Spotting in the system. It explains the communication and security services integration, from root of trust to cloud communication. Finally it analyses what the future of voice and accompanying services and devices will look like what solutions will be needed.

In visual focus capturing for ambient assisted living an algorithm to obtain the visual focus of a person in order to perform brain-controlled service of devices is developed. The main target groups for which the solution is designed are elderly and disabled people; however the algorithm may be applied to diverse scenarios including logistics, delivery, surgery and more. The work faces current trends and technologies for capturing the visual focus of a person and for brain-controlled building automation systems. The motivation behind the work is to combine the two aforementioned fields and create a simple, cheap, efficient and offline system which is able not only to target the main target groups, but also a wide spectrum of other potential users and application areas. A thorough research and concept verification have shown the optimum approach to be using a brain-wave-reading headset combined with a camera module for sensing barcode tagged objects in the area of visual focus.

Lidar sensors are essential for autonomous vehicles and most ground moving robots. In their short scan cycles, these sensors generate a large number of points containing information that can be used to detect obstacles in the surrounding environment. While the process of extracting information, detecting and tracking relevant objects and filtering noise or road reflections is complex, it needs to be reliable and accurate. We explain how to preprocess raw point clouds from Lidar sensors in MATLAB to generate detections for conventional trackers that assume one detection per object per sensor scan, define a cuboid model to describe kinematics, dimensions and measurements of extended objects being tracked with a joint probabilistic data association and an interacting multiple model approach, and finally generate C code from the algorithm and verify execution results.

Edge Machine Learning is crucial to IoT. It's unreasonable that we will deploy 50 bn dumb devices. By enabling the intelligence to run onboard the device, one can see the real-time, granular sensor data instead of blunt averages that are sent to the cloud, which enables instant automation, and less dependency on connectivity. This enables individual learning per device, which is extremely valuable for many features. However, sometimes you want to learn from many. From the entire or sub-set of the installed base. This is why Ekkono introduces Federated Learning as an extension of Edge ML, enabling the correlation of ML models, i.e. compare and combine what you've learnt rather than the data. This saves a lot of bandwidth by just sending the model, while still getting better granularity as the model is trained on all the high-frequency (even kHz) sensor data. This is smart use of computation infrastructure, and enables a lot of new opportunities that will be addressed in this session.

EEMBC created the MLMark™ benchmark to standardize inference-performance metrics on so-called "edge devices," devices with a small thermal-design power (TDP) envelope. Compared to historical benchmarks targeted at CPUs, machine-learning benchmarks differ significantly. First, the key element in ML/DL is the graph, not C/C++ source code. Second, the translation of the graph to the hardware depends on the framework, which exposes optimizations for tuning the graph, and the SDK which may contain proprietary strategies for configuring the hardware resources. Third, machine-learning accuracy generally decreases as performance increases due to optimizations. Therefore, a performance score is meaningless without its associated accuracy score. Further complications include parallelism—such as concurrency and batching—which have a nuanced difference depending on the application. This paper will explain our methodology for addressing these variables, as well as results and future-proofing.

The most expensive part of bringing an electronic product to market is R&D, followed by quality maintenance through production. We visit China frequently. Just like anyone else, we always have an eye on competitor offerings. Lately, especially in cost-sensitive markets, we observe a new trend. We not only compete with genuine competitors from Europe or the US but also with Chinese copies of their products, which undersell the actual manufacturers substantially. Chinese government increased the efforts to fight deceptive counterfeits. Fighting patents infringed by non-deceptive counterfeits still is much harder. The paper provides insights into the Chinese counterfeit microchip industry. It discloses how products are cloned and discusses options to fight violators on a legal base directly and through their customers’ products. The paper also describes technical countermeasures, all based on a real-world example on the process of a patent infringement case for a foreign company in China.

Too often, semiconductor authenticity is impossible to guarantee; the counterfeit market for chips is sizable and growing. According to a 2012 US Govt. report, 1M+ counterfeit electronic components were used in 1.8K instances affecting military aircraft and missiles. Industry Week sized the 2019 WW fake semi market at $75B. Recent incidents of counterfeit parts in commercial devices include defibrillators, airport landing lights, IV drip machines, and brakes for high-speed trains. A counterfeit chip in a tank could feed details of payload to adversaries. Rogue code in a fake semi could shutdown the air supply of an airliner. A counterfeit chip could be used to shut down a car in a ransomware attack. The many ways a counterfeit chip could catastrophically affect end systems are too numerous to count. This paper addresses: • how and why chips are counterfeited • issues that counterfeit parts present to chip designers, OEMs, and the general population • solutions for reducing the problem

Embedded products are expected to last for a long time and often under extreme use cases such as automotive, industrial, Military and Aerospace. The presentation will demonstrate the necessary trades-offs Silicon foundries have to make to ensure the operating duration of the product meets the customers requirements. Thus, topics like the affects of temperature, power and performance, silicon aging and other silicon reliability factors will be briefly discussed. The audience will leave knowing the physics limitations when manufacturing silicon for more sensitive Embedded markets.

Bitcoin popularized its public ledger that we call “blockchain.” Blockchain is in wide use today for more than cryptographic currency. Applications vary from ensuring software is delivered securely to processing government issued visas and licenses. These applications ultimately serve humans. As such, people trigger an interaction with a blockchain. To date, machine triggering is not well known. However, development tools exist that enable an embedded engineer to lock down electronic hardware-based keys that can be used when blockchain operations are machine triggered. This opens whole new applications for blockchain that are embedded in nature. Now, internet appliances and equipment in factories, to name a couple, can be included in blockchains so that their operations can be logged and tracked. This paper presents what can be developed, how it is developed, and forecasts some applications that the new electronic hardware enables in the anticipated explosion of blockchain-based applications.

The majority of manufacturing companies expect significant, high or very high improvements through the IT integration of their supply chain partners, the majority are planning relevant or high investments in this area. The ability to network with value-added partners has proven to be a significant competitive advantage for most companies. A much-discussed approach to the creation of transparency with regard to value chains is the use of blockchain technology. The aim of this paper is to present a generic and therefore reproducible, scientifically based procedure for the configuration of an industrially applicable blockchain. In particular, it is crucial to find out which scientific preliminary work is necessary for this. The anticipated goal is to be achieved with the research methodology of Ulrich and with the aid of models (Description model, Explanatory model and Design model). A comprehensive morphology of Blockchain technology will be presented.

Smart systems and devices are connected to the real–and analog–world in order to achieve a maximum benefit for society. Therefore, alongside massive digital functionality, analog will always be necessary at least at the device‘s interfaces. Designing such analog parts, however, differs significantly from digital design. Ever more powerful synthesis tools improve the productivity of digital design engineers while analog design suffers from still largely manual design. The reason is found in the complex kind of constraints and objectives that are to be considered simultaneously. Generators are designer-friendly tools which automate frequent analog building blocks in a user-defined way. This paper presents the application of generators in a 22nm SAR-ADC design. It discusses the advantages of generators over manual iterations regarding design productivity and presents an outlook how to further improve generators as well as their integration into the analog design flow.

The original room-sized analog computers were programmed using paper drawings and manual cable connections. The Apollo IC is the first digitally programmed analog computer, implemented in a 4x4 mm2 CMOS IC and capable of solving problems with high speed and extremely low power. The high level programming language of an analog computer are the differential equations describing the problem. The solution to each problem is realized by the proper interconnection and calibration of the analog computer elements in such a way as to produce the desired results. Deducing from the equations the right interconnections and implementing these in the analog computer circuitry is the role of an analog computer compiler. Such a compiler has been developed for the first time by MIT researchers for the Apollo IC analog computer. In this paper we will present the integration of the analog computer hardware and software and present examples of the steps to derive solutions for real life applications.

Heterogeneous Integration (HI) has grown substantially in recent years within the semiconductor industry. Computing and communication devices were the early adopters of HI via advances in assembly technology. Learn how Analog Devices is using HI and its iPassive technology to change the Precision Conversion Playing Field. This present will use application examples to illustrate how a system level hardware designer can leverage solutions based on HI to advance precision performance at the system level and significantly reduce form factor.

In this presentation, a disruptive software, called ID-Substrate, which is developed by intento design is presented. ID-Substrate provides an innovative approach for systematic detection and prevention of all types of substrate noise coupling. This is achieved by modeling lateral propagation of minority and majority carriers inside a piece of doped substrate. This model is automatically extracted for a complete chip and simulated in a Spice in just few minutes. The spice simulation reaches an accuracy comparable to standard TCAD simulations.

The design effort for upcoming integrated circuit and package technologies is rising because of increasing complexity in production. To cope with that situation it is essential to reuse pre-qualified elements for handle complexity. For package technologies this becomes more and more apparent. Looking at the requirements for 5G applications for package technologies it is no longer feasible to start from scratch. So it becomes more and more import to use prequalified elements for a technology and build your general system based on a construction kit of radio-frequency blocks. This paper deals with the implementation of RF-structures for manufacturing and characterization and establishing of a set of elements, that are pre-qualified and are available as building blocks to be used for future projects. For upcoming package technologies it is getting more and more important to include these devices into so called Assembly Design Kits (ADK) to enable designs by potential customers.

The Trusted Platform Module (TPM) 2.0 is a standardized hardware-based security solution for securing industrial, automotive, building automation and others. Developers who want to use the TPM 2.0 can make use of the TPM Software Stack (TSS), which is a middleware software that is standardized by the Trusted Computing Group (TCG). The presentation shows the application and advantages of the TSS Stack by explaining use cases and the integration with the TPM and the TSS Stack. The TSS Stack standard and the architecture of the API layers are shown to explain the technical mechanisms of the software. The benefits and enhancements of the different layers are presented and the integration in typical Linux-based systems and microcontrollers is outlined.

Software is the prime target for attacks. Unprotected software can be easily digitally copied, allowing the pirate to sell the software for their own personal gain and well below its intended value. In cases where software is linked with a machine or control system, the electronic and mechanical parts are copied together, allowing the attacker to create a counterfeit copy that looks and operates just like the original, but requires just a fraction of the cost of the original to build. Effective protection technologies exist today that encrypt software code and create licenses which can be bound to a secure element in the target system. The software would then run only on the designated machine, device, or embedded system and provide the functionalities associated with the license, safe from any sort of hacking. Complementary license and entitlement management systems allow software-powered businesses to meet customers’ demands in a granular way and in turn expand their reach globally.

A common target for attacks on system security is the persistent memory that stores the code of that system. IoT devices are targets for such attacks. This paper describes how secure memories can be used to improve the resilience of a system against network attacks by; 1. Providing access control mechanism to protect the device firmware as well as user content stored in it including master and region-specific access control mechanisms 2. Supporting DICE to detect modification to the device configuration or user content stored in it including concepts to enable attestation for multiple chips These points are discussed in the context of the concepts that are being developed in the CyRes work group: 1. Mapping of CyRes primitives into Memory Devices 2. Secure channels between server and memory – how to operate a bus slave device as an endpoint of a secure channel 3. Applicable use cases

To attest to the boot state of a device, the TCG has determined that three roots-of-trust are required. Two of those, the Roots of Trust for Storage (RTS) and Reporting (RTR), are traditionally provided by the TPM. Without a TPM, as is common in many smaller devices such as IoT, manufacturers lack the needed mechanisms to perform reliable measurement and attestation. The purpose of this research is to present very low overhead options for integrating the needed functionality around crypto acceleration hardware already common today. Moreover, it presents options for optimizing the overhead down to a level potentially suitable for the smallest of devices This presentation will cover both an overview of the research and the activity within the TCG.

Industrial automation equipment maker typically depends on proprietary RTOS or hybrid Linux-RTOS approach with proprietary Ethernet driver to support real-time communication. In recent years, substantial progress has happened in Linux kernel, notably preempt-rt merged into mainline, standardized TSN traffic shaping control interface, in-kernel qdisc and per-packet Tx time setting. Linux community has started to extend the use of eBPF and XDP to build new high performance packet processing. XDP ZC, introduced in Linux 4.18, has impressively achieved very high throughput in 10G & 40G Ethernet. This paper describes how Linux TSN capabilities are used to support OPC UA PubSub over TSN and how very tight cycle time is achievable by extending XDP ZC socket capability with per-packet Tx time setting while IT traffics flow through legacy socket. This approach serves as technology mirror for other real-time communication stack (e.g. PROFINET) to adapt into TSN capability in Linux mainline.

In automotive audio applications, Ethernet is used to reduce the wiring effort for connecting a centre unit with an audio endpoint. Transmitting audio via Ethernet requires real-time capabilities which can be achieved by using the AVB protocol including features such as gPTP, SRP and traffic shaping. Audio endpoints based on TDM/I2S to Ethernet bridges that include multi-channel audio amplifiers and microphones are highly demanding in terms of overall latency and timing requirements when supporting applications like echo or noise cancellation. To fulfil the overall timing and latency requirements, and to ensure low system cost, efficient hardware solutions are required for the data flow from Ethernet to TDM/I2S and vice versa. To achieve maximum flexibility a general-purpose CPU core should be added also. The presentation will explain the applied approaches to implement a powerful and cost-efficient audio endpoint ensuring audio transmission according to standards like IEEE 1722-2016.

Time Sensitive Networking (TSN) is an extension of the IEEE 802.1 standard, enabling deterministic real-time communication in standard Ethernet networks. Time synchronization is a basic building block of TSN and a key requirement for every device in a TSN network. To provide a high-precision time synchronization of network devices, the IEEE TSN working group is revising the 802.1AS standard which is based on the existing Precision Time Protocol (PTP, IEEE1588). This became necessary to fulfill new requirements and restrictions of TSN. Although the revised standard is not finalized yet, the key changes are known. This paper discusses the main working principle of PTP including its hardware requirements. Its major contribution is a review of ongoing research activities of the TSN community with respect to high-precision time synchronization.

Security is an increasing concern in industrial systems. From the many aspects of security this paper focuses on the real-time performance impact of integrity protection and confidentiality at the fieldbus level real-time cyclic IO traffic. This traffic has unique hard real-time requirements that cannot be directly met by using well established IP networking solutions like TLS, DTLS or MACSec. In this work, we quantify the additional latency introduced by adding integrity protection and confidentiality to cyclic IO frames using principles outlined by Profinet over TSN on commercially available embedded industrial system-on-chip (SoC). Our results show the additional latency and processing load intruduced by adding security to cyclic IO packets. Profinet over TSN is used as an example but the results apply for other real-time datagram protocols such as OPC UA PubSub over raw Ethernet.

Time-Sensitive Networking (TSN) Ethernet technology much sought after by industrial automation equipment maker who heavily depends on real-time communication with bounded low latency. To achieve this on today RTOS, it requires a systematic approach that combined both TSN capable hardware and software innovation which offers network sockets for mixed-criticality traffics in an OT/IT network and data path innovation such as Tx & Rx ring passing between user-space and Ethernet controller DMA engine without data-copy e.g. UDP Zero Copy methodology in FreeRTOS. This paper uses Zephyr, a Linux Foundation open-source RTOS project, as technology case study to explain networking stack Tx & Rx frame buffer zero-copying & ring management and how TSN traffic shaper (802.1Qbv & 802.1Qbu) configuration could be populated over LLDP and YANG/netconf client. All above are key components to ensure scalable TSN network configuration deployment and end-to-end communication with bounded low cycle time.

Time synchronization is a key necessity for Industrial systems as factories move towards modernization with Industry 4.0 paradigm. In this paper we introduce Time GPIO feature, an innovative time synchronization technology that enables customers to precisely synch clocks with external devices. We plan to elaborate on the Synch In and Synch Out hardware functions that can enable customers to save costs and achieve low ns precision without the need to add an external component such as FPGA for timing synch. We will elaborate on the Time GPIO API's that are being developed and how customers can plan to use these API's in their solutions. The paper will also highlight use cases in Industrial and Energy segments such as Test and Measurement for Distributed networks as well as on premise edge servers, TGPIO port to TSN network, etc.

The use of multicore SoCs in embedded designs is on the increase and there are multiple incentives for this design decision. In this technical webinar, we will review the available multicore architectures and show how they are leveraged with a selection of software configurations. The use of multiple operating systems on heterogeneous multicore devices will be explored, and how this facilitates the design of systems with multiple time domains - basically real-time and non-real-time components. Additionally, the concept of mixed criticality will be introduced - a design approach for systems where safety and certifiability are key requirements. Certification effort and costs can be minimized, while still meeting the requirements of the worldwide authorities.

Android's use in the automotive industry has been silently increasing over the past few years. While Android's use in a car inherits quite a few things from classic Embedded Android, there are several automotive-related additions to the Android Open Source Project (AOSP) that are worth a closer look. This session will cover the Car System Service, the internal Car system APIs, the built-in Car Apps, the car-related HIDLs and car-related specific features such as Exterior View System, Vehicle Properties, Audio, Power Management, wear leveling and boot time optimizations.

In many embedded systems, Realtime is an important requirement, but at the same time, Linux is the preferred Operating System because of its large ecosystem and ease-of-use. However, Linux is not natively a Real-Time Operating System. Many of the latest Arm-based SoCs provide different kinds of Arm cores on the same die. We are specifically looking at the i.MX 8 from NXP. The chip provides several Cortex-A cores but also Cortex-M microcontrollers which are well suited to handle Realtime Tasks. I will compare this new approach with the Linux Realtime Patch, and Hypervisor solutions. I will present benchmark data showing the performance which can be achieved. Further, we are looking into the ease-of-use of the different approaches. I will demonstrate how to use Visual Studio Code to develop on Cortex-M cores. At the end, you should have a good understanding of what Realtime solution makes the most sense in your next project.

AUTOSAR develops a new approach to cope with the challenging market trends in the automotive industry such as internet access in cars, highly automated driving and V2V-communication. The result is an intelligent, flexible infrastructure SW named AUTOSAR Adaptive Platform. The platform runs on high end computing hardware and supports parallel processing on many core systems and GPUs. Consequently, it can also be used to support high bandwidth communication, is able to host AI applications and will therefore support deep learning and video stream processing in real time. The POSIX nature of the operating system enables the deployment of customer applications during live time so that software updates over the air are complementing the feature set. Platform Health Management, ISO conform diagnostic functions and the support of E2E-protection for sensitive communication channels as well as a common methodology for E/E standardization and security improvements are further functions.

Every team making an Internet-connected embedded device knows they're going to need a solution for delivering software updates. Every security engineer knows that software update systems are a very high-value target. And yet, we still see new devices come out with no way to update, or update systems that repeat mistakes of the past, like relying solely on transport security or not planning for rotation and revocation of software signing keys. The automotive world is starting to come around, using the Uptane framework for delivering firmware updates to vehicles. What can the IoT world learn from this? In this talk, we will briefly introduce the threat model of Uptane, and how it provides both resistance and resilience against known attacks on software update systems. Then, we will show how Foundries.io adapted libaktualizr (an open-source Uptane-based client for automotive use) to suit IoT devices, and the surprising development workflow efficiencies that were gained "for free".

Functional safety standards including IEC 61508 (generic safety related systems), ISO 26262 (automotive) and IEC 62304 (medical devices) generally categorise systems and subsystems in terms of their criticality, where an integrity level for a safety function is dictated by the properties of associated hazardous events. The decomposition of Functional Safety Requirements permits less critical subsystems to be assigned lesser integrity levels to help to reduce cost and effort, but it must result in design elements of sufficient technical independence. The whole of the assignment of integrity levels implies an assumption of separation such that the most critical subsystems cannot be compromised by those of lesser criticality. For a connected system in particular to be considered functionally safe, the separation between subsystems is paramount. This paper will discuss the role of secure software coding techniques in ensuring that such separation cannot be compromised.

Did you ever face challenges deriving concrete strategies and actions from the ISO 26262 standard upfront in a project to achieve compliance and avoid mid-project changes to these foundational areas? The ISO 26262 standard for functional safety provides high level guidance on the development of automotive electronics and electrical systems, including embedded software. At the MathWorks we have observed that the room for interpretation of the standard can be both a useful and a burden. In this presentation, you will find out more about different challenges when developing software to be compliant with the standard. These challenges are related to freedom from interference, testability at different software architecture levels or other requirements. Based on MathWorks frequent customer engagements you will see strategies how these challenges can be addressed by using modelling patterns that are proven in use by our customers.

Designing and implementing a safety related multicore system is certainly not a trivial task. First, there is the need for an appropriate software architecture, which is considering safety considerations. Then, the code needs to be written according to this specification and finally there is the need to assess the result in terms of safety requirements. Together with the FZI Research Center for Information Technology and the company HighTec, we investigated if a modeling and code generation tool for safety related systems can be realized using open source solutions such as the Eclipse Modeling Framework (EMF). In this presentation, we will demonstrate how the developed tool unifies architectural and safety aspects and how an entire multicore runtime environment can be generated using EMF. We will also focus on the technical aspects of the multicore runtime environment and show how multicore software architectures can be realized using standard RTOS features.

Increasingly used in industrial applications from sensor signal preprocessing to predictive maintenance analysis, Deep Neural Networks (DNNs) can potentially be part of safety-critical final applications. While existing literature explores similar scenarios in the automotive safety domain, no specific work is available for industrial applications which have both different applicable safety standards (IEC 61508 vs ISO 26262) and implementation paradigms (software vs hardware). In this paper we will give a full, exhaustive survey of all the considerations related to the use of software-implemented DNN solutions in a IEC 61508-compliant final application based on a general-purpose microcontroller. Existing issues and limitations in regards to compliance and regulatory requirements will be highlighted. Finally, potential research and methodology vectors requiring further investigation will be discussed.

Since the early 1990s, federated avionics architecture - where one computing resource executes only one application, is being replaced by Integrated Modular Avionics (IMA) architectures. IMA architectures employ a partitioned environment that hosts multiple avionics functions of different safety criticalities on a common computing platform. This provides for size, weight, and power savings via denser functional integration. Several cores integrated onto one device allows more functions to be integrated together on one processor and in one piece of equipment. Hence aerospace equipment suppliers are interested in using Multi-Core Processors (MCPs) in their systems. However, with the shift to multi-core processors, compliance to safety requirements is becoming critical. The development and use of increasingly complex electronic hardware by the aviation industry for more of the safety-critical aircraft functions is creating new safety and certification concerns.

A lot has been done in the recent years in the area of function safety. Safety standards have been revised and extended, there are plenty of vendors for certified hardware and software, and there are plenty of different approaches to design functional safe systems. There is common sense that a safety system needs to be build on a safety certified hardware. But this is not correct, it is very well possible to use uncertified, off-the-shelf CPUs to build a safety system on them. This paper describes what the safety standards say about certified hardware and how to monitor the correct behavior of the hardware. It is shown what that means for the correct design of the safety software and which software methods and techniques need to be used to monitor the hardware in a standards compliant way.

MISRA rules are classified as decidable or undecidable, depending on the theoretical ability of a static analyzer to answer the question "Does this code comply with this rule" with "yes" or "no" in every case. Undecidable rules require information about the program semantics, e.g., what value an object holds, or whether a particular program point is reachable. The well-known Rice Theorem proves that in such cases no static analyzer can give a correct yes/no answer in every case. However, depending on the depth of an analyzer it is possible to answer the questions with different levels of assurance: unsound analyzers can report false negatives (missed violations) and false positives (false alarms). With a sound analyzer the absence of false negatives can be proven, i.e., no violations are missed. The talk explains the concept of soundness, discusses to which degree the undecidable MISRA C rules can be covered by automatic tools, and what level of assurance can be reached.

The Barr Group's Embedded C Coding Standard is, for coding standards used by the embedded system industry, second only in popularity to MISRA C. However, the choice between MISRA C:2012 and BARR-C:2018 needs not be a hard decision since they are complementary in two quite different ways. On the one hand, BARR-C:2018 has no incompatibilities with respect to MISRA C:2012 and, modulo programming style, it defines a subset of C that, while preventing a significant number of programming errors, is larger than the one defined by MISRA C:2012. On the other hand, concerning programming style, whereas MISRA C leaves this to individual organizations, BARR-C:2018 defines a consistent programming style aimed at increased readability. As a result, BARR-C:2018 can be seen as a first, dramatically useful step to C language subsetting that is suitable for all kinds of projects; critical projects can then evolve toward MISRA C:2012 compliance smoothly while maintaining the BARR-C programming style.

To provide a common set of rules that supports innovative software development, MISRA and AUTOSAR announced that their industry standard best practices for C++ will be integrated into one publication. MISRA — an organization comprised of vehicle manufacturers, component suppliers, and engineering consultancies — published MISRA C++ in 2008. This first release of MISRA C++ provided expert guidance for the development of safety-related software in ISO C++ 2003. As the C++ language had advanced considerably since the publication of MISRA C++, AUTOSAR enhanced the guidelines to make the standard applicable to C++14. The new MISRA standard will be applicable to C++17 and will merge the AUTOSAR guidelines with its own established best practice to develop a single standard for safety-related C++ development. This session gives a unique inside view of the possible outcomes of the MISRA C++ working group.

MISRA C is a programming standard that is focussed on writing safe, secure code using the C language. This is achieved by the definition of a number of guidelines that lead the developer away from operations and constructs that may compromise the safety of the code. By taking a fresh look at the standard, this session concentrates on the benefits of MISRA C in an additional priority in embedded software development: the writing of clear and maintainable code.

There are many static analysis tools available to assess code compliance with MISRA guidelines. But the identification and rectification of violations flagged by a tool represents only one part of the compliance process. Step back from the analysis of violations and it is easy to see bigger questions about the process as a whole. MISRA’s document “MISRA Compliance:2016” receives much less press coverage than the language subsets, but it is invaluable in understanding how the information highlighted by the static analysis tool of choice relates to that bigger picture. This paper will discuss several key points raised by the MISRA compliance document. It will reflect on the necessity of a “do it right” mindset even before the detailed demands of the language subsets are considered. And it will conclude that such a mindset cannot be the exclusive prerogative of the critical systems community, because a system does not have to be critical before there is a need for it to work reliably. On first acquaintance, the MISRA language subsets can appear overbearing with their myriad of rule definitions and explanations. They might also appear impossibly draconian. The very first rule in MISRA C:2012, for example, dictates that “the program shall contain no violations of the standard C syntax”, and yet the perfectly justifiable use of compiler extensions is widespread. Closer inspection however reveals a deviation procedure, for those occasions when “it may be necessary to deviate from the guidelines given in [the standard]“. Deviations must be recorded and authorized, provided there is justification to do so – as for the compiler extensions. This paper will discuss the principles and mechanism surrounding MISRA C deviations. It will discuss how the deviation procedure is intended to work, and how it prevents the unscrupulous from implementing deviations for mere convenience. And it will conclude that the standard as a whole really can apply to almost any critical system.

Despite formal guidance by the MISRA committee achieving MISRA coding compliance is not an easy endeavour. This is especially true for legacy projects or software originally not written with functional safety or MISRA/CERT/AUTOSAR compliance in mind. For legacy projects management and engineering are often overwhelmed with thousands if not millions of findings when first applying MISRA rules to an existing code base. A strategy towards compliance is needed. In this talk we present how novel software analytics and data visualization techniques can assist embedded organisations in developing such strategies towards a practical roadmap for MISRA compliance. We also show how analytics and risk data help to break down the barrier between management and engineering, enabling higher project success rates. We provide the audience with guidance on how to apply this knowledge to their own compliance activities and which investigations can help building their own compliance roadmap.

Implementing artificial intelligence in automated vehicles follows different development paradigms than the traditional design of embedded systems. With much of the function not realized by explicit programming, but rather by automated code generation resulting from training with extensively labeled data sets, the question arises what kind of tools and development systems need to be available for this implementation. We will introduce a framework and tooling infrastructure that covers the entire development process: from data collection to labelling support to machine learning and system deployment. We focus on issues of validation, as much of the automatically generated software is safety-critical, and address automated simulation as a key aspect of this validation before the software finally hits the road. (This is intended as a session keynote by request of the Program Committee.)

It’s a matter of when, not if, fully autonomous cars will be part of our everyday commute. As the ADAS enabled cars of today slowly evolve into the autonomous cards of tomorrow, designers face challenges on how best to architect the system to ensure the car meets the requirements in terms of safety, reliability, security and of course, functionality. Successful solutions will be a delicate balance of compute power, thermal efficiency and cost. Increasingly, autonomous vehicles, all be it with safety drivers, are appearing in city streets. These systems tend to be “proof of concept” vehicles which will no doubt bare little resemblance to the end product once they have been optimised and made production ready. This presentation will take a top down approach to the problem and look at some of the decisions, challenges and trade-offs facing designers. It will discuss current systems and look at the challenges facing designers in order to turn a concept into a product.

Automated driving is getting massive attention from industry, road authorities, and consumers. Tests are crucial for convincing the market that autonomous vehicles are reliable and secure. Virtual validation provides an efficient and systematic way to test these systems. Such validation requires a simulation environment that closely resemble real-world environments and include control algorithms, options for creating traffic scenarios, sensor models, and representations of vehicle dynamics. In this paper, we first show different ways of generating virtual driving scenarios. These ways include designing virtual driving scenarios using both scripts and graphics user interfaces, importing scenarios from preexisting libraries, and generating scenarios using data recorded from on-vehicle sensors. In a second session, we explain how to programmatically create variations of an existing scenario. The generated scenarios can be used in closed-loop simulations to model and test controllers.

Neural networks (NNs) have demonstrated impressive performance on visual recognition tasks relevant for autonomous drones or personal air-taxis. So, their application to visual problems like object detection and image segmentation is promising, and even necessary, for autonomous flight. Yet, for safety-critical applications, it is generally assumed to be difficult or impossible to demonstrate correctness and robustness of NNs. In this talk, we argue that the design and verification of NN-based systems need new methods to assure safety and performance. Over the last months, we have partnered with EASA (European Aviation Safety Agency) to explore concepts for design assurance and certification of NNs in airborne systems. We will present an overview of our framework for quantifying uncertainty associated with NNs and discuss model explainability, generalizability and adversarial attacks. Finally, we will explore how these ideas fit in with current certification processes such as DO-178C.

Moving to autonomous driving, the requirements of automated driving developers in validation rise. The presentation covers main technical obstacles dealing with multi sensorics (covering Camera and Radar) systems and tool requirements and gives an insight into best practices to overcome the challenges. B-plus shows the best practice workflow beginning from raw sensor data extraction via the recording of multiple sensor data streams to the ingest into a data center or a cloud. It covers technologies and mechanisms considered from low Level sensor data streams up to Cloud infrastructures in data Centers.

Deep convolutional neural networks (CNNs) offer a good alternative for classical sensor fusion algorithms, when relying on pre-processed sensor data. Recent research shows promising results, where feature-level inputs are used to generate an environmental model. To be applicable in real-world, the models have to be implemented on automotive ECUs with strict constraints. Therefore, existing approaches are analyzed in terms of computational burden and modified with modules known from SqueezeNet. Finally, the trade-off between parameter and MAC count reduction versus the degradation of fusion quality is evaluated. Fusion quality is measured with metrics known from pixel-wise classification tasks, like IoU and pixel accuracy. This paper shows that proposed grid fusion network preserves same level of fusion quality, while being compressed by factor of 5.7 in parameter size and 4.5 in MAC count. This compression allows proposed networks to run on Synopsys EV61 CNN engines in real-time.

As the RISC-V instruction set architecture (ISA) matures, and SoCs are developed using RISC-V, there is a need to address the new verification challenges of RISC-V based SoCs. For SoCs built using traditional processor cores, the verification tasks are well known, as the starting point is based on the assumption of “known good IP.” The new verification challenges include verification of the RISC-V processor IP; verification of the processing element (PE) containing the RISC-V core(s) (especially relevant in SoCs with a fabric designed for AI processing); connection of the processor itself or the PE to the network on chip (NoC) and multiple PEs communicating through the NoC to each other. In this paper the verification challenges for RISC-V SoCs are presented. Specific verification flows including new test and instruction stream generators, reference models and metrics are presented in detail including the results of using these flows on real processor IP and SoCs.

Verification of system-on-chip (SoC) designs containing RISC-V processor cores is challenging. The cores can come from many sources, so they must be vetted for compliance to the instruction set architecture (ISA) specification. Beyond the ISA, optional features, custom extensions, and microarchitectural implementation must also be verified. The SoC team must guarantee proper integration of the cores and the entire chip must be screened for design issues that could hinder proper operation. Further, both cores and SoC must be checked thoroughly to ensure that no hardware Trojans or security risks are present. Only formal methods can provide full proofs for all these verification tasks and build confidence in the integrity of the design. This paper describes a formal-based methodology to meet these challenges, summarizes previous work on multiple RISC-V cores and SoCs, and presents previously unpublished results.

Due to the increasing complexity of SoC, rendering on-chip debug and design bring-up is more difficult and time-consuming. Conventionally, debugging the application running on an embedded multi-core CPUs is done using an IDE tool connected to the JTAG interface. With such IDE, a user often doesn’t have controllability and observability of internal buses of the SoC. And very often they are limited by the JTAG bandwidth for real-time trigger, capture and in-situ intervention. This paper will show how developers can save time by using the SoC’s in-built instrumentation to trigger and capture od desired AXI bus transactions between master-slave pairs like DMA to DDR. The developer can capture the instruction trace of multicore RISC -V processors based on the address range. The configuration can not only be achieved over JTAG but also done by using application running on the RISC-V processor. For large traces, the trace data can be routed to DDR memory or any memory connected to AXI slave.

System on Chip (SoC) development teams today can choose for their hardware/software projects from three key dynamic verification engines for pre-silicon verification and early software development– simulation (at the transaction- and signal-level), emulation and FPGA based prototyping. Each of the engines provides different performance, fidelity and debug flexibility that needs to be considered carefully in the context of design bring-up and engine cost. Using examples from recent customer case studies, as well as comparing user requirements, this presentation will analyze the different options that development teams have to balance the usage of dynamic engines. We will illustrate how such balancing results in the optimization of verification throughput and enables software development at the earliest possible time during a project. We will extend the analysis to show how to combine different levels of abstraction in simulation and emulation for even further optimization.

Abstract: Software is wonderfully flexible. On many of today’s embedded systems software can be changed at a moment’s notice and updated to systems world-wide over-the-air. This characteristic makes software the ideal choice for implementing algorithms on so many systems. But software is both slow and inefficient. And there are times when performance and efficiency requirements trump software’s flexibility and risk mitigation. This session will describe the use of high-level syntheses to “compile” C++ descriptions of algorithms into synthesizable RTL as a way to migrate them from software to hardware, targeting either ASIC or FPGA. We will discuss practical ways of interfacing between the new hardware and software. We will look at the performance of algorithms implemented in hardware as compared to software. And we will explore the differences in both power consumption and energy use in implementations in hardware as compared to software.

This presentation will address the challenges of software development for pre-silicon processor and SoC designs. Embecosm has for many years developed compiler toolchains and more recently operating systems well in advance of customer silicon being available. We'll explore all the different open source techniques we use to model hardware and develop software for new silicon designs, including: - modelling peripherals and processor cores using Verilog, Verilator and QEMU. - producing custom toolchains based on GCC and LLVM - porting and testing bootloaders and operating systems - writing and testing device drivers - providing an SDK for software development teams We will demonstrate the on-going work that Embecosm is doing to define and support an open source 'software development framework' that is uniquely targeted at pre-silicon developers and SoC designers. Throughout we'll illustrate the talk with real customer examples using the RISC-V architecture and software ecosystem.

Manufacturers are investing heavily into IoT to launch new digital services, create innovative business models and drive efficiency based upon sensor data. As data volumes are skyrocketing, cost and latency challenges have been shifting the focus increasingly from cloud-centered IoT architectures towards edge solutions. Against this background, three key questions arise for IoT software development: 1. How can edge functionalities efficiently be developed and integrated into IoT cloud architectures to ensure future-proof, secure and scalable IoT solutions? 2. Which edge development frameworks/ platforms are available for this task and what are their respective benefits/ limits? 3. How can edge distributed computing help to create cost-effective, fault-tolerant and scalable systems? The presentation answers these questions in depth, categorizes the variety of existing offers, suggests a pragmatic selection process and shows latest trends in distributed computing by means of a live demo.

The immediate challenge to achieve Industrial Convergence requires a higher level of performance, so that AI-decision making is done in real-time and at the edge of the manufacturing line. Industrial Automation equipment needs to monitor and take actions for improving manufacturing throughput, efficiency, and to reduce operational costs. These intelligent factories require AI technology to make critical real-time decisions based on information gathered from a host of intelligent manufacturing machines. These robots and intelligent sensors enable the Industrial Internet of Things (IIoT). A new class of ultra-small PLCs is required to provide real-time edge-based decision making. An example of this technology in action will be presented.

Arm Cortex-M processors have been shipped in more than 45 billion chips for a vast range of applications, from industrial sensors to wearables. This growth has exploded more so in the last few years due to the significant rise in connected products for diverse markets. AWS IoT provides broad and deep functionality, spanning the edge to the cloud, so customers can build IoT solutions for virtually any use case across a wide range of devices. With designers of IoT applications under extraordinary pressure to build innovative solutions quickly, affordably, and satisfy many design requirements, how can the IoT continue to scale across a growing number of use cases? The session provides a tour of a simple path to developing secure Cortex-M based IoT devices with Arm and AWS, and how together, the collaboration provides choice and scalability for IoT developers.

EdgeX Foundry is an open source, hardware and OS independent, edge platform backed by more than 70 companies that provides a scalable and flexible platform that addresses the multi-protocol needs of the edge. It’s a platform that already speaks multiple OT protocols. It’s a platform that can make sensor and device data available to a variety of cloud, enterprise and analytic solutions. No IoT platform, not even EdgeX, does it all. In this session, learn how EdgeX’s SDKs allow you to create custom device/sensor connectors or get data to your application without changing the application. Learn how the EdgeX architecture supports replacing major chunks of functionality with your own when warranted. And even though EdgeX can support near-real time but not real time use cases, learn how EdgeX can be extended to address real time needs.

The IoT landscape is exploding and there’s an urgent need for standardized, interoperable and proven end-point security. Years away, right? Wrong. Introducing IoTopia In this presentation GlobalPlatform, a non-profit industry association driven by approximately 90 member companies, will deliver insights into its new initiative, IoTopia. The initiative: - Proposes a common framework to standardize the design, certification, deployment and management of IoT devices. - Aims to be testable and meet vertical requirements by building on foundational pillars: secure by design; device intent; autonomous, scalable and secure onboarding; and device life-cycle management. - Will be a simple but executable framework that is standards-based, industry-wide and able to evolve as security capabilities and requirements change. - Will provide the opportunity to support tiers of security as well as certification in desired verticals.

The digital transformation of the manufacturing industry opens opportunities for factory floor equipment, creating value out of their data shared with local IT applications or through manufacturer IoT Platform. IT and OT communication are merging in automation devices. What are the impacts of IT security requirements to traditional fieldbus communication standards and development processes? How to implement new IT communications capabilities local (OPC/UA, MQTT) or cloud based, combining the traditional OT low latency data exchange with open cloud connectivity, or setting up an own IoT Platform with security, users and update managements? Market Inputs and hints for industrial device manufacturers implementing their networking interface up to the IoT Platform, to manage the diversity and complexity of the functionalities, specification and certifications for a future proof value creation platform without compromising the security and performance required by the industrial application.

Designed specifically to address the challenging requirements of commercial and industrial environments, Bluetooth mesh networking allows manufacturers of all sizes and geographies to join a globally interoperable ecosystem of devices that work with each other out of the box, enabling the widespread adoption of truly efficient large-scale device networks. This session will look under the hood of the Bluetooth mesh specifications, exploring some new capabilities soon to be available and helping answer some of the most common questions about how to embed Bluetooth mesh into IoT solutions and products. You'll also hear from implementers and experts with first-hand experience successfully commissioning and implementing Bluetooth mesh networking technology in multiple environments as they share their assessment of the protocol’s performance, scalability, and latency.

Bluetooth is a ubiquitous communications protocol, with countless applications in consumer electronics, the home, industrial automation, and asset tracking. With BLE Mesh now added as a network layer, there are even greater opportunities for simultaneous control and monitoring of hundreds (or even thousands!) of devices. These new capabilities come with added complexity for developers. In this session, noted industry expert Brian Bedrosian will discuss the key benefits of BLE Mesh and educate attendees about design considerations for BLE Mesh networks including: the node architecture and elements, Server and Client models, certification, as well as considerations for software development kits (SDK) and mobile applications. Using lighting control as an example, attendees will come away from the session with a practical understanding of how to build successful BLE Mesh products.

Bluetooth Mesh is a promising wireless technology for building automation. At the same time, KNX is a well-established building automation system that has a huge installed base. Specifically, the strength of KNX lies in its proven semantic models. These models are the foundation for interoperability and the implementation of larger systems. The presented project demonstrates how a user can easily connect a new Bluetooth Mesh system to a well-established, wired KNX building automation system. Notably, the project achieves this through a self-developed stateless gateway, which allows controlling Bluetooth Mesh devices from the KNX network and vice versa. As a result, it is possible to leverage existing management systems from KNX building automation systems in Bluetooth Mesh networks. Furthermore, the project validates this concept using Home Assistant, a well-known open source home automation platform and demonstrates, that heterogeneous KNX and Bluetooth Mesh systems are feasible.

Device-to-device range is an important factor to consider across many IoT solution areas. This session will address some of the most common myths concerning Bluetooth range, discuss the key factors that influence the effective range of a reliable wireless connection, and offer design tips for developers to exploit Bluetooth features and capabilities to achieve the optimal range for their specific use case.

Optimizing Bluetooth Low Energy (BLE) applications for low energy consumption can be challenging, so understanding BLE and the underlying system-on-chip (SoC) architecture is important to enable extended battery life. This session provides insight into the Bluetooth Low Energy modes of operation (such as Advertising and Sleep) and different ways to minimize the power consumption of the entire system by providing the right inputs to the stack and how to take advantage of all hardware features of the wireless SoC device. This includes MCU-specific low-power techniques as well as Bluetooth stack-level low-power optimizations. The session will include a real-world application showing the battery lifetime benefits after applying the available low-power design techniques. An additional example will demonstrate a benchmarking framework and how to decode the performance readings obtained with this communication software for edge-node devices.

The Bluetooth specifications enable advanced security features to accommodate a wide variety of embedded applications and systems. This session will provide implementation guidelines to help embedded developers understand the range of security options available when developing with Bluetooth, as well as some best practices to follow when securing Bluetooth devices and solutions.

This presentation attempts to give an overview of the Yocto Project from a bird's eye perspective.

As you contemplate how to put together the system software for your next Embedded Linux project you will probably be wondering which is the best path to take? Use a Linux distro such as Debian, (or another of your choosing), or create a custom operating system using Yocto Project (or Open Embedded or Buildroot). At first sight, Debian looks easy, especially if you are using a Raspberry Pi, a BeagleBone or another board with a pre-installed Debian-derived system. So, why go to all the trouble of replacing it with Yocto? In this talk I will show you the strengths and weaknesses of each approach, using real-world use cases as examples. Spoiler alert: my conclusion is that … it all depends what you want to do. Debian is great for fast implementation and proof-of-concept, but for long term maintainability and control of the platform, you need Yocto. Now you need to come along to see why I believe this to be so.

Ubuntu Core, is enabled on a wide range of devices from leading manufacturers like Dell, Rigado, Intel, Qualcomm, Samsung and NXP. Using a pre-enabled and certified board greatly reduces the cost and time of appliance development. Customers focus entirely on their applications, with the base system enablement and security maintenance provided by Canonical throughout the lifetime of the device. Customers do not need to integrate and rebuild the OS for security maintenance, but they can control the distribution of Canonical updates to Ubuntu with their own certification and testing regime. Ubuntu Core brings the principles of continuous deployment right to the edge. Snap channels enable automatic beta testing and canary updates. Travis integration and a multi-architecture build service ensure that the same CI/CD train can support identical apps across x86, and ARM architectures with both 32 and 64-bit snaps and simultaneous update releases.

The Time Sensitive Networking (TSN) extensions provide real-time capable and deterministic communication for regular Ethernet. Not only does the network has to be deterministic, the end stations have to act deterministic as well. Therefore, the end stations are often driven by bare metal or special real-time operating systems. However, Linux is becoming more and more popular for embedded devices these days. In this contribution we will show why Linux in combination with the PREEMPT_RT patch is a good choice as operating system for TSN end devices and what Linux offers for real-time networking today.

Knowing how to debug the Linux kernel is an essential skill for every embedded Linux developer. And debugging the Linux kernel with printk messages is a common technique (often a good one). The problem happens when we only know this debugging technique. How to debug a kernel oops message? How to trace and understand the kernel execution? How to identify and analyze a buffer overflow? How to identify a memory leak or a deadlock in kernel space? In many situations, there are more effective kernel debugging tools and techniques, including KGDB, ftrace, addr2line, eBPF, kmemleak, and so on. In this presentation, we will go over these and many other very useful tools to identify and fix problems in the Linux kernel.

The last 20 years have seen a tremendous surge of new technologies and capabilities emerge from open source software. These open source building blocks have become increasingly attractive as the base for innovative new products. Safety critical applications are now using them as well, but we lack infrastructure to assess when this software is safe to use, that can keep up with the rate of change of open source development. This talk will look at some of the challenges and approaches to building trust and confidence in open source used in safety critical software coming to new products. The approaches taken by 3 open source projects (Linux, Xen, Zephyr) will be discussed and contrasted.

To secure devices connected to the IoT, features like an immutable device identity, secure boot with Root of Trust, secure key storage and hardware crypto accelerations paired to a high-entropy random number generator are becoming an elementary requirement. Due to a growing number of security incidents surrounding the IoT, legislators are pushing to mandate minimum security levels (e.g. according to IEC 62443-3-3 or CSPN) for certain IoT devices or application areas. This session will show how an integrated secure element can not only help to address these soon-to-be-essential imperatives, but how it can add additional benefits like secure software updates or secure debug unlock, both of which cannot be easily achieved with an external secure element. For IoT device implementers, a brief summary of the key features of a secure element will be delivered along with the author’s view on how integration can help reduce cost while significantly increasing security levels in product design.

Platform Security Architecture (PSA) Certified was announced as a major industry initiative to improve IoT device security at Embedded World 2019. PSA’s rapid adoption is based on freely published architecture documents, open source code and an independent evaluation scheme to build trust into IoT devices, data and services. At Embedded World we will unveil major new aspects to PSA Certified: 1. 2020 version of PSA certified Level 1 covering governmental IoT requirements 2. New evaluation flow for easier OEM device level PSA Certification 3. Announcing the first chip vendors to get PSA Certified Level 2 for their PSA Root of Trust 4. Providing a preview of PSA Certified Level 3 that will provide a substantial level of assurance and robustness for device security This talk will explain how chip vendors and software platforms are using PSA Certified to make it easier and quicker for OEMs to develop IoT devices built on sound security principles and independent evaluation.

With the autonomous revolution underway in the auto and industrial markets, edge nodes are becoming cyber-attack targets. Software updates, remote capture of diagnostic data, and communications between remote endpoints and infrastructure are becoming increasingly common and prone to major security threats. A challenge with semiconductor advancement is that as geometries continue to shrink, eFlash becomes more difficult to embed within an MCU on a Hardware Security Module (HSM). When eFlash is offloaded, it is in a more vulnerable state, making it critical to have a secure boot process, and the content on the devices must also be trusted. During this session, attendees will learn about the development challenges and security requirements needed for next-gen devices as memory moves off the HSM and in some cases becomes a hardware root of trust. Additionally, use cases will be covered including: cryptographically secure storage, fast secure bootup, and secure Firmware-Over-the-Air Updates.

In recent years, there have been several exploits of wireless protocols based on the relay and replay attack vectors. For example, car access systems today are based on low-frequency radio technology and are vulnerable to these attacks. With the increasing trend of automobiles being stolen using these attack vectors, there has been increased urgency in the market to provide a secure and robust wireless solution for solving this problem. Round trip time of flight (RTT) is a ranging security method based on the Bluetooth Low Energy 2 megabits PHY that helps developers to secure against a variety of attack vectors such as replay and relay attacks. Using RTT, it is possible to verify that a peer is both trusted and physically located nearby. In this discussion, we will investigate these attack vectors and discuss how RTT can be used to help enable secure range bounding solutions.

A Public Key Infrastructure (PKI) is a strong security fundament to secure device-to-device communication. However, the management and the processing of public key certificates in small embedded devices is a major challenge. There are different protocols available for automated certificate enrolment with a PKI. Among them, Enrolment over Secure Transport (EST) is one of the widely used and more secure enrolment protocols. Constraint devices use Constraint Application Protocol (CoAP) for message transport. This paper focuses on the evaluation of such a certificate provisioning protocol called EST over secure CoAP(EST-Coaps), which is primarily designed for constrained IoT devices. The deployment model incorporates the field devices, a deployment agent and a credential authority. Field devices need to interact with the Credential Authority (CA), in order to obtain Site Credentials. More precisely, this paper analyses the performance of EST_Coaps in terms of scalability and security.

Critical Real-Time Embedded Systems for industries such as railway, aerospace, automotive and energy face multiple challenges including a growing need to support mixed-criticality applications, power and timing restrictions and a need to develop and test these complex devices and the accompanying software. The approach adopted by the SAFEPOWER project, an EU Horizon 2020 program, was to develop a SoC architecture including a NoC plus the hypervisor to support spatial and/or temporal isolation of the various functional units. Advantages of this hardware/software architecture include the increased isolation provided by using both spatial and temporal isolation and the adaptability of this architecture to changing conditions. This paper discusses the virtual platform methodology employed by SAFEPOWER. Unique tools developed to provide observability into the hypervisor-based system are described, as well as the methods for providing timing and power estimation with sufficient accuracy.

As the number of connected devices grows, there will be a greater demand for sensors to capture data to share between devices. Traditional sensors include three primary functions:Power for the electronics, a sensing element, and processing for data formatting, analysis, and communication. As the demand for additional sensing nodes increases, the cost to scale traditional sensor networks limits the deployment of sensors in some applications. New wireless sensors can untether the sensing from the power and processing functions.These wireless, battery free sensors utilize energy harvesting and a shared power and processing block.These sensors complement electronic sensor networks, and reduce the cost to scale in certain applications.A shared sensor hub is used to aggregate data from multiple sensors and provide cloud connectivity to the cloud for monitoring, analytics, and action Applications include predictive maintenance,healthcare,automotive,digital farming,datacenters and more

Sigfox is one of the popular LPWAN technologies of the Internet of Things. Like many other wireless protocols, it is mainly used with batteries, which leads to important maintenance costs and slows down its acceptance. Allowing such systems to work on harvested energy will facilitate their use. In this presentation, we will explain the way Sigfox works, its advantages and disadvantages with regard to other popular LPWAN technologies. We will then talk about the energy requirements of a battery-less Sigfox node and introduce our design. Finally, we will discuss the results and performances of the system.

To achieve simultaneous data communication and wireless power transfer (WPT), this paper describes how Würth Elektronik has developed a combination of WPT and near field communication (NFC) coils in a single device. First, this paper describes the general setup of the WPT and NFC system. Constituent parts of the system are analyzed by simulation and verified by measurement. The design of the resonant tank for the wireless power components to achieve high efficiency is described. The optimal distances between the NFC-transmitter and –receiver coils at different power levels are examined. The methodology for minimum reflectance and impedance matching of the NFC coil to the NFC IC is described. The interoperability of the WPT and the NFC coils is investigated. The trade-off in the separation of combination-transmitter and combination-receiver coils is considered. Finally, some typical applications and the advantages of the system compared to conventional NFC systems are discussed.

mmWave technology opens up an entirely new spectrum for mobile communications and brings with it the promise of 5G’s dramatic data speeds. However, it also brings several new challenges, in particular mmWave signals quickly deteriorate when passing through buildings, wall and trees. At the same time, the high data rates require a high-speed connection to the mobile carrier’s network. To solve both of these problems, the industry is embracing the deployment of 5G small cells throughout buildings. High-speed Ethernet coupled with Power over Ethernet (PoE) technology will form the backbone of these indoor cell networks. The new 802.3bt PoE standard brings this concept to reality by delivering 71 W of power to the small cell device. This session will cover the basics of this new standard, the new power supply topologies needed to realize these new power levels efficiently, and how various PoE distribution schemes being debated for small cell deployments.

This paper discusses a novel communication scheme for porting SPI output from MEMs accelerometers over long distance for condition-based monitoring (CbM). Common challenges in designing a wired physical layer for MEMs include EMC robustness and data integrity. However, when extending clock synchronised SPI over long cables, and combining power and data on the same twisted pair wires (phantom power), several additional challenges are presented. Challenges discussed in this paper include managing system time synchronisation, and filter design and simulation for shared power & data architectures. Filter design is especially important where the designer cannot add Manchester encoding to remove signal DC content. Passive Filter component selection is discussed with available communication design windows and experimental measurements over cabling. Temperature effects on system performance is measured, and EMC immunity is quantified. All concepts are verified on a wired CbM platform.

Transferring reliably CAN, LIN, RS232/485 protocols over powerline requires significant sophistication due to the power lines unpredictable communication channel response and noise. The power lines as communication channel become relevant in many industries where wires are of concern due to weight, cost, space and reliability. This presentation describe semiconductor solutions for CAN, LIN, RS232/485 protocols at data rates up to 1.4Mbit/s. The new DC-LIN ISO 17987-8 standard address the LIN over DC powerline communication. A semiconductor implementation will be presented. Arbitration over powerline is a great challenge due to the power line noises. An innovative solution implemented in a CAN over powerline device that meets automotive and aerospace industries requirements will be described. Although several communication techniques mitigate with these difficulties, the solutions are costly in terms of silicon size. The new devices mitigate with the cost of the wires it replaces.

On the one hand, many standards in software and systems engineering are based on assumptions that are currently no longer fulfilled: Systems are treated as closed, static artefacts, with no autonomy and typically the underlying development process is assumed to be traditional and phase-oriented. On the other hand, systems in many domains – e.g. Industry 4.0, autonomous driving, energy management – are different: They are open, they do dynamic adaption in an autonomous way and they are large and heterogenous. This influences the systems engineering solutions that are to be applied in order to master these challenges. The talk will discuss these challenges and will present recent solutions.

An overview on how modern Agile techniques are changing the way embedded software is being developed. This tutorial is ideal for anyone who is either new to Agile, considering using Agile or even has experience in working with Agile methodologies and practices with embedded software or firmware developments. It will clarify the Agile landscape, covering both process based aspects, such as Scrum and various techniques, including Test Driven Development (TDD) and some of the underlying foundation principles, such as Continuous Integration (CI). As part of the discussion, we shall look at some of the modern-day tools that help apply Agile techniques(e.g. Docker) and finally look ahead to the current gaps and where embedded systems offer particular challenges to the use of Agile techniques.

When the world expects from you developing more and more complex systems and decreasing your time-to-market you can ask the question: How to achieve both in parallel? We learned from the professionals in these areas, namely, SW houses and automotive companies how to do it. SW houses use agile development to provide MVP and get feedback as soon as possible, automotive companies use A-SPICE to build-in functional safety in complex systems. Connection of both methods gives new opportunities. The presentation will show how to implement efficiently A-SPICE to new projects that use Agile Development method. It will be demonstrated what are the advantages and disadvantages, and how it fits to the R&D team within the production company.

Half of the project errors can be traced to poorly written requirements, and specification and design errors become exponentially more expensive to fix the longer they go undetected through subsequent lifecycle phases. However, system engineers struggle to find techniques to improve textual requirements quality, especially compared to other areas like hardware & software development. And many critical projects still fail because of unclear and conflicting requirements in functional and safety specifications. Work has been done recently to provide system engineers with guidelines (INCOSE, IREB, IEEE 29148, EARS) to substantially improve requirements quality and greatly reduce the time spent in both writing and reviewing them. During the conference, you will learn practical techniques and best practices to consistently write high-quality requirements faster while avoiding ambiguities and similarities. Superior functional and safety specification quality in 2020 can be achieved!

How can we perform systems engineering tasks associated with standards like ARP 4754 & ISO 26262 part 4, while ensuring the key derived requirements filter down to the implementation? Performing large scale system design and upgrades is a task of ever-increasing complexity. Traceability and synchronization across all design levels is key to streamlining large scale development programs. However, there is often a missing link between systems engineering and design implementation in top-down design process. In this presentation it will be demonstrated how to bridge the gap between systems engineering and implementation in a top down legacy systems upgrade project. The example case study shall follow the update of key system level requirements & architectural modifications down to identification of the required design implementation. Finally, a system level trade-off analysis shall be performed to assess the high-level impact of the upgrade on the complete system.

Software development standards applicable to safety- or cybersecurity-critical applications (including ISO 26262, SAE J3061, IEC 62304 and IEC 61508) usually demand bidirectional requirements traceability. DO-178C is typical with its requirement for trace data to: 1.Enable verification that no source code implements an undocumented function. 2.Enable verification of the complete implementation of the low-level requirements. It is essential not only to confirm that all requirements are fulfilled, but also to ensure that there is no surplus code that could suggest feature creep, logical flaws, or even a malicious backdoor method. This paper will explore the implications of bidirectional traceability for a geographically disparate development team. It will discuss the challenge of providing data on a “need to know” basis, providing perspectives according to job function. And it will discuss the project management overhead associated with maintaining that traceability.

In today’s hyper-competitive global economy, customer satisfaction is increasingly being driven by software. Software is the primary controller of the human interface with electronic devices and substantial parts of the core functionality. Application life cycle costs have increased dramatically as software complexity and application sizes have increased. Cambridge University published a report estimating the global spend on software maintenance and bug fixing at US$300 billion, and multiple studies peg the maintenance costs of software at twice the original development cost. During this same period, new tools and processes have been developed to make software development easier, but buggy software persists. The answer to improved quality is not a new tool or a new paradigm, it’s simpler than that! In this paper we will discuss some steps that any software project can take to improve quality by examining the testing process itself and suggesting areas where improvements can be made.

All electronic systems carry the possibility of failure. An embedded system has intrinsic intelligence that facilitates the possibility of predicting failure and mitigating its effects. This paper reviews the options for self-testing that are open to the embedded software developer. Testing algorithms for memory are outlined and some ideas for self-monitoring software in multi-tasking and multi-CPU systems are discussed.

The accuracy of the system, as is usual for other measuring systems, must also be ensured. If, for example, analogue inputs and outputs are used for the simulation of sensor values or the measurement of currents, precise specifications are absolutely necessary, since for safety-critical functions there are usually exact requirements for error detection thresholds and error detection times. For the reasons mentioned above, it makes sense to add self-test functions to HIL test systems. The automated testing of all inputs and outputs of the HIL test system makes it possible to dispense with manual maintenance work. For the execution of the self-test it is necessary to integrate an independent measuring system and an independent signal source. Based on this automated self-test, it is also possible to carry out calibration and adjustment. With the approach described here, the integration of expensive measuring equipment into the test system can be dispensed with.

Embedded technology has revolutionized sectors of the industry in ways that were previously never thought possible. For this reason, product testing is becoming increasingly important. Ensuring that our embedded technology functions properly is a priority for most companies, regardless of where that technology happens to be located. In this presentation we will explore white box and black box techniques for testing embedded systems, talk about system and performance testing, and summarize some of the unique testing requirements and approaches for real-time embedded systems. Topics include static and dynamic analysis techniques, exploratory testing, equivalence partitioning and boundary value analysis, and hueristics based testing methods.

Structural testing is an important acceptance criterion for safety-critical embedded and cyberphysical systems (as in Aerospace, Transport, and Critical Infrastructure). To cover all established requirements and, vice versa, all code to be deployed makes testing very difficult and costly. We elaborate on a solution that validates the conclusiveness of high-level functional tests on fully-integrated safety-critical applications in a non-intrusive fashion. Our approach performs an online analysis of hardware processor trace data in real-time to establish coverage proofs on-the-fly during test runs. It offers deep insights into the completeness of both the tests and their underlying requirements. Establishing the validity of tests on a high functional level reduces the effort enormously that is required on lower, less integrated levels to achieve and justify conclusive coverage statements. The savings achieved by our approach in the development process will be demonstrated and quantified.

According to safety standards, the development of safety critical systems requires well-defined functional and non-functional tests The quality of testing is crucial for the safety and security of an embedded application. Compliance with the required test methods of the standards and the test quality can only be checked manually in a review. Mutation testing automatically checks the error detection capabilities of existing test cases and provides a useful measure for the test case quality. This presentation describes an efficient approach to mutation testing. The C/C++ code to be tested will slightly be mutated at error sensitive locations so that typical programming errors will be present. If the available unit and integration tests detect the mutation, they are scored to be useful. Applying this method on existing test suites reveals weak test cases and achieves a better quality in testing and helps fulfilling the requirements of the standards.

Machine learning technology is being deployed in many areas of embedded systems. This technology is composed of many hardware and software building blocks. These building blocks can be used to create integrated optimized machine learning enablement for different processing elements of embedded systems such as cores, GPU's. DSP's and various forms of machine learning accelerators. In this presentation an architecture of machine learning building blocks is presented and an industry case study of how to apply these building blocks to embedded system end nodes as well as the edge. A concept for how to integrate these core building blocks into the cloud for machine learning model creation and deployment is also discussed.

Machine learning is impacting every market including deeply embedded applications. Intelligence is rapidly moving to endpoint devices with increasing demand to enable ML in devices that are the most resource-constrained. Security, latency and bandwidth issues for audio and video use-cases demand ever-increasing processing capability in endpoint devices. This presentation will talk about how AI applications and Neural Networks can be efficiently implemented and accelerated on the extremely low-power, low-area endpoint devices. The talk will also show Arm’s collaborative approach, utilizing open source software for ML solutions. This approach will enable developers to efficiently tackle the challenges in this space and make it easy to create and deploy ML applications.

We present how deep learning acceleration is performed on the Kalray MPPA3 manycore processor. Each core is tightly coupled with a coprocessor that leverages the core load-store unit to transfer data at the rate of 32 bytes per memory access. The coprocessor then uses these data blocks as either left or right operands of a matrix multiply-accumulate unit, while taking care of formatting them in a uniform way with a fixed number of rows and a variable number of columns, depending on the size of the elements. A standard trained neural network is taken as input by the KaNN code generator. The generated code executes one layer at a time, in topological sort order of the network. For each layer, execution is distributed across the compute clusters allocated to this inference. Network parameters are read from DDR memory and multicasted through the processor RDMA NoC, while the input and output activations of the current layer are distributed across the local memories of the compute clusters.

On-device AI brings unprecedented capabilities and opportunities to endpoint devices with improved privacy, security, and reliability. Deploying on-device AI must consider various constraints of memory, power, latency, and cost. Therefore, neural network optimizations become critical for exploiting hardware features, reducing memory footprint and improving computation efficiency. In this talk, we present techniques for model optimizations such as pruning, clustering and quantization for enabling energy-efficient AI on resource-constrained devices. Optimization cascading is achieved where each technique preserves the preceding attributes. Under different optimization objectives, exhaustive search for finding the optimal sparsity, quantization and clustering levels for each layer is compute intensive and impractical. To counter this, we have developed efficient techniques to navigate through the large search space, thus enabling trade-offs between accuracy, latency and compressibility.

As Deep Learning (DL) enters embedded devices, developers wonder what hardware they should use for these algorithms. Besides CPUs, embedded GPUs have appeared recently, but the market of dedicated ASICs for DL showed a real revolution in the last two years. Mostly American and Chinese companies - big players like Intel and Google and many start-ups - have developed chips that outperform embedded CPUs and GPUs by far. Moreover, new terms appear in the articles. Spiking Neural Networks (SNN) are about to be used in first practical applications, and analog electronics including memristors/ReRAMs claim a place in the zoo of DL hardware. All of these species are refered to as neuromorphic hardware. Our presentation will explain why dedicated chips are better suited for DL than CPUs and GPUs, how DL can be carried out in analog electronics and what is actually an SNN. Moreover, we will present some examples of commercial chips and ongoing research activites and projects.

Deep neural networks (DNNs) have become state-of-the-art for a wide range of applications including computer vision, speech recognition, and robotics. The superior performance often comes at the cost of high computational complexity. The process of creating and training a DNN model is difficult and labor-intense, and the resulting models rarely optimized for running on embedded devices. Automated techniques to improve energy efficiency and speed without sacrificing application accuracy are vital. Companies like Amazon and Facebook showed that compressing weights or squeezing the architecture can reduce the model complexity by a factor of 20-50 while maintaining almost identical performance. The field of 'deep compression' has become a dedicated branch of research. Technical support for such optimizations is starting to be available by a growing set of tools. This talk gives an overview of deep compression techniques and tools with example applications.

IP assets within companies are often under-utilized due to a variety of impediments. The most common are: discoverability, suitability, quality-assessment, asset acquisition, and support. Larger companies often have access to third-party IP; but the terms-of-use, licensing and internal contacts for those IPs may be unclear (leading to redundant and/or delayed acquisition). Some designers may have never designed for reusability and the requirements for publishing for other design teams are not well understood. This often leads to (de-facto) sharing practices such copying assets from network file systems. Loss of design expertise, the exact origin of IP, and its suitability for a given technology or purpose is (therefore) lost. Traceability for functional safety adherence is fundamentally compromised. In order for IP reuse to be fully leveraged within an enterprise, a culture of sharing and re-use needs to be fostered and supported by management, engineering practices and software tools.

At sub-7nm regime, chip designs must go through hundreds to thousands of steps and tasks before shipment. Many tasks are data and simulation intensive, thereby demanding significant amount of resources and time. Unlike conventional methodologies relying on experiences to manually handle data and extract models, recent advances in machine learning techniques enable the successful applications in various complex tasks to accelerate modern chip designs, ranging from architecture to post-silicon validation and tuning. The goals are to reduce the amount of time and efforts to process and understand data through automatic and effective learning and enhancing from examples. Electronic design automation (EDA) must deliver “design based equivalent scaling” to help continue essential industry trajectories. A powerful lever for this will be the use of machine learning techniques, both inside and “around” design tools and flows. This paper reviews opportunities for machine learning with a focus on entire SoC design flow from Architecture to IC physical implementation to post silicon validation. We also review and discuss several application cases of machine learning techniques, including architecture level modelling , pre-silicon hotspot detection through classification, post-silicon variation extraction and bug localization through inference, and post-silicon timing tuning through iterative learning and optimization, to leverage the potentials and inspire more future innovations.

Designers are increasingly incorporating third-party standards-based IP in their designs but are facing several challenges. With the increasing number of IPs included and with each becoming more complex to address market demands, the effort to integrate is taking much longer; while project schedules are getting shorter. Companies are spending time on integration effort rather than on product differentiation. This presentation, in the context of actual uses of IPs such as I3C, embedded PCIe and USB, will cover the benefits of implementing a custom IP subsystem, composed of pre-designed subsystem architectures, blocks, and test-benches, and verified in the context of the SoC. Also, address prototyping challenges to quickly gain functional know-how. This type of customized interface IP subsystem provides extra functionality and value over simply integrating a PHY and controller, while reducing overall cost, design time, and effort with a clear pathway to prototyping and demos.

Due to their hardware architectures, FPGAs are optimally suited for the implementation of machine learning algorithms, but so far there are no suitable tools, which could make the implementation in the FPGA easy. A frequently used solution to this problem is the implementation of machine learning algorithms with Open Compute Language (OpenCL). While OpenCL supports the development of machine learning algorithms, it also adds unnecessary overhead to the FPGA netlist, limiting the performance of the FPGA. The Institute for Embedded Systems developed a framework for the development of fully interconnected dense layers and 1D and 2D-convolutional layers. Networks defined in Tensor Flow or Keras are transferred to the framework. The implementation is done directly in VHDL and is optimized for synthesis into an FPGA. This enables nonlinear signal processing with neural networks in real-time directly on the FPGA without the use of an embedded CPU.

The presentation will give some background information on a SEU-TID IP-Core for monitoring of single events and aging effects especially for flash-based FPGAs using floating gate transistors. The concept was verified by real measurements in medical radiation environments. A new special implementation IP of a ring oscillator is used to show the asymmetrical degradation for TID sensitivity and charge loss of transistors. It was simulated with a real-number modelling methodology (VHDL-RNM). This special implementation is also applicable for ASICs and SRAM-FPGA technologies. In addition a new IP architecture was developed to detect also aging effects due to normal wear-out mechanisms like electrical and thermal stress and charge loss of floating gate transistors. The results of accelerated life and stress tests will be presented.

The nowadays requirements to process highly computation- and storage-demanding workloads is rapidly exceeding the traditional capabilities of server architectures. To this extent, the computational storage paradigm came into play. This approach revolves on the off-loading ability of the reliability/power consumption/performance management routines that are usually demanded in the storage components. In enterprise environments, this could be enabled by an FPGA architecture that shares the same interconnection fabric (usually PCIe) of the Solid State Drives constituting the server storage. In this presentation, we will show an example of an FPGA-based Neural Network Accelerator that relives the burden of the computation of a reliability management algorithm through an AI-approach, namely the Moving Read Reference, from the Solid State Drive controller. The results promisingly shows a low power consumption, and a very low latency that does not interfere with the normal SSD behavior.

Cybersecurity represents a dark cloud overshadowing the “smart grid” modernization of the existing electrical grid system that enhances customers' and utilities' ability to monitor, control, and predict energy use. The need for a secure enterprise-level architecture in defending against potentially devastating blackouts is widely acknowledged, but the role played by securely coded devices is easier to ignore and yet vitally important. This paper will argue that as part of a defence-in-depth security strategy, monitoring smart devices deserve particular attention because they access data that is critical to smart grid operation. It will suggest that many of the most appropriate quality assurance techniques for secure coding are well proven in the field of functional safety. And it will advocate that the structured development approach promoted by IEC 61508 provides an ideal framework for the proactive development of a secure application.

Power plants, radar systems, traffic lights, communications and weather systems have been part of everyday life for decades, which have made security and longevity paramount. Currently, these systems are built from scratch, with little re-use of existing software building blocks. This model drains resources and leads to fragmentation and duplication of effort. In this talk, The Civil Infrastructure Platform will showcase how it works with other open source projects to develop a super long-term supported (SLTS) open source "base layer" of industrial-grade software that enables the implementation of building blocks in civil infrastructure projects. This session will feature how open source software powers smart cities.

Modern elevator applications increasingly involve components interconnected using standardized or proprietary field bus systems. These systems grant the local access to the elevator embedded networks and would require remote connectivity component e.g. a gateway(s) to grant the remote access to these networks e.g. to perform system diagnostics or submit data for remote processing. An effective elevator management would require, additionally, the appropriate component condition monitoring to prevent operation breakdown. This presentation gives insights into the solutions provided by CAN in Automation. The condition-monitoring concept of CANopen lift can be extended for any other CANopen application. CANopen IoT concept from CiA offers a gateway services from TCP/IP networks to CANopen networks. The CANopen IoT in combination with the condition monitoring could be a link from embedded CANopen network to a Web-based component monitoring and diagnostic stations.

This non-technical two-hour Internet of Things (IoT) tabletop exercise benefits business and technology leaders and regulators in the Energy, Oil and Gas, Transportation, Healthcare, Financial, and Manufacturing sectors. Through discussion of a simulated cyber IoT incident, you explore required capabilities and processes. You learn how to leverage the cloud for security, high availability, incident response, and continuity of operations for systems that include IoT. You also discuss the advantages of cloud security and resiliency over traditional on-premises environments to understand your opportunities. Finally, the effectiveness of international cybersecurity frameworks in improving an organization’s posture is highlighted. No laptops required.

Our operating environments are constantly changing; instead of dictating system behavior we need to teach system behavior. With today's means of teaching machines, we must leverage vast amounts of compute and storage to more accurately and automatically define how we shape decision algorithms. In this talk, you will learn how we can effectively acquire the vast data sets and apply the right compute against fieldbus derived data, which in turn enables the future of predictive maintenance. 1. Objective and Overview. 2. 1) Learn how to reduce, transfer, and curate fieldbus protocol resources... 3. 2) Define fit-for-purpose algorithms. The curated data feeds the algorithm to optimal refinement given the current data state. 4. 3) The mechanics for relaying the valuable data model are employed to distribute the new understanding to the device fleet so all systems can take advantage of the new learning. An inspection on canary testing is evaluated. 5. Demonstration. 6. Conclusion.

Cloud computing has become pervasive and this compute capability is driving increasing requirements of edge computing. Bringing compute power near the source of the data becomes paramount to address scalability, cope with RT constraints, latency and security of emerging apps. In order to overcome those challenges, software developers are using many technologies where RTOS, virtualization and containers are cornerstones of the architecture. We'll review: - the challenges of implementing heterogeneous systems. - a real use-case of a critical function combined with cybersecurity features based on a system architecture comprising an RTOS, Yocto-based Linux and Docker containers running on both System-On-Chip platform and OpenStack-based platform. - the underlying software components, the development tools and testing methods used for performance tuning. - the lessons learned in relation to the overall system architecture, and the integration of individual hardware and software components.

Bluetooth as specified in versions 5.x is entering new application spaces – The good old Bluetooth is made ready for the future of a hyper-connected world. Features like long-range, high-speed, audio, mesh, or direction finding are some of the cornerstones. Over the last decade, testing of Bluetooth LE with a wired direct test mode (DTM) was best suited for accurate, easy-to-use and repeatable testing of any device or module. In order to deal with devices of tomorrow there is a need for new test approaches. For example, it becomes difficult to connect a modern device via cabling for testing and get accurate results from over-the-air testing of a wired device. The paper/presentation will elaborate latest features of Bluetooth LE and related test challenges and will give insights into new innovative test approaches to meet today’s testing requirements for accuracy, efficiency and easy use for all phases of the product live cycle

With more than 1 billion Bluetooth audio devices shipping each year, Bluetooth has become the default way to experience audio. By 2023, 90% of all new speakers will include Bluetooth, and when given the choice, over half of all consumers purchasing new headphones choose Bluetooth over wired. In this session, the Bluetooth SIG will share its unique perspective on the history of wireless audio as well as an early look at soon-to-be released new features in the specification that will unlock new use cases, advance existing ones, and set the stage for the next 20 years of wireless audio.

Auto manufacturers have been adding Bluetooth Low Energy (BLE) capability for numerous applications including, for example, passive entry passive start (PEPS) which employs a key fob that can send a signal to a smart key module to trigger the mechanism to unlock the doors. This system typically has a master smart key module and multiple slave modules that are physically distributed around and in the car. System designers would like to design one hardware board with identical software for the slave modules so that installation in the car is agnostic of the position, however since the hardware and software of the slave nodes at installation time is identical, a scheme is needed for the master module to assign a unique address to each slave node after the modules are installed in the car. Currently, a wired communication interface is used to address all the slave nodes; We will discuss how to address each slave node using BLE techniques in order to remove the wired communication interface.

Bluetooth can be used for many types of location service and it’s an area forecast to experience the biggest growth in the next few years, with 431 million location related devices shipping in 2023. In 2019, Bluetooth acquired a new capability which allows the direction of a signal to be accurately determined using one of two methods known as Angle of Arrival (AoA) or Angle of Departure (AoD). Come to this session and hear about this Bluetooth location services and the new direction finding feature, how it works and the uses it’s likely to be put to.

The Bluetooth 5.1 specification introduced a new direction-finding feature, which enables sub-1-meter accuracy asset tracking and indoor positioning applications using Bluetooth wireless technology. The new direction-finding feature supports multiple methods for determining signal direction including angle-of-arrival (AoA) and angle-of-departure (AoD) technology. Prior to the release of Bluetooth 5.1 software, traditional RSSI-based direction-finding solutions provided only 3-5 meter accuracy. This session provides an overview of the Bluetooth direction-finding feature and discusses the architecture of indoor positioning and asset tracking solutions and how to implement and deploy direction-finding solutions for real-life environments.

Ever since its inception, interest in using Bluetooth technology in industrial manufacturing applications has been increasing, thanks, in large part, to findings by ABB Corporate Research back in 1998. Bluetooth based time-critical control applications with moderate latency requirements have been developed and in use by several companies for over a decade. This presentation will give an overview of low latency deterministic control using Bluetooth technology, present the basic elements required to increase the acceptance of Bluetooth by the manufacturing industry, provide insights to what research has found, highlight existing applications that industrial control companies have developed, and look at what future enhancements of Bluetooth might bring. In addition, the presentation will provide a quick introduction into specific developments, originating from Bluetooth technology, in short range, low latency, deterministic control.

FullMetalUpdate is a fully open source solution based on Yocto to deploy and manage containers on embedded Linux systems. In this talk, Cédric will introduce the different mechanisms that are used to create and deploy containers with the Yocto build system and OSTree in an automated fashion. In a second part, it will be shown how FullMetalUpdate can also be used to assign specific hardware resources to containers, and enable communication between them by way of virtual networking. As part of this talk, Cédric will present a demo showcasing how these features can be used with FullMetalUpdate in a scenario including several containers such as a Qt application, an SQL databse and a MQTT client.

Fog/cloud computing is mostly based on an x86 architecture and place high demands on security, connectivity, computing power and AI support. Edge computing or sensor/actuator nodes, on the other hand, require more deeply embedded features such as the direct connection of sensors and actuators as well as real-time capabilites. For this purpose, a microcontroller is used and connected via a serial connection with a powerful host processor. Heterogeneous SoC combine both on a single chip, enabling completely new solutions with higher performance and flexibility but reduced space and cost. We show the power of interprocessor communication between an Cortex-M4 and A7, and how the different distribution of peripherals affects data throughput and system utilization. Using the example of Linux and FreeRTOS, we also examine the software features of interprocessor communication. With an M-Bus stack implementation on the STM32MP1 we show a concrete implementation example of the above methods.

Over the past years support for the different Arm Mali series of GPUs has been crystalizing in the Open Source space. The first few steps towards supporting some Arm GPUs hardware were taken in 2012, and was aimed towards the low-end Mali 2/400 series of GPUs. While this work showed that it was indeed possible to create an Open Source driver, it would be a long time until the Lima driver actually materialized. Very much unlike the Open Source driver for the Mali 2/400 series of GPUs, support for the Mali-T and Mali-G series started to be looked at only in 2017. Since then development has progressed at a furious pace. The mesa driver, Panfrost, has now been merged and provides initial support for the T700 and T800 series of GPUs based on the Midgard architecture. In this talk Robert will walk you through the process of creating a driver for a new GPU, from reverese engineering to upstreaming and then finally shipping a new Open Source driver.

Container technology, also known as a container, is a mechanism to package up an application with all of the parts it needs, such as libraries and other dependencies, and ship it all out as one package. This method makes containers a self-contained unit that can run anywhere and also isolates them with other such running container instances. Control groups (cgroups) is a Linux kernel feature which allows processes to be organized into hierarchical groups whose usage of various types of resources can then be limited and monitored. runC, a tool for launching and running containers according to Open Container Initiative (OCI) specifications. In this talk, Saurabh will present how cgroups is used in the container environment and how the system resources are controlled for a group of processes in the container. Using runC on the Linux system, he also demonstrates the usage of cgroups for controlling key system resources such a memory, cpu and network for a group of processes in the container.

Car companies and their suppliers long ago learned how to take raw steel and turn it into a finished product. When software first entered the car, it was all closed source, but at the turn of the twenty-first century the complexity of software in cars exploded. Even so, OEMs and Tier Ones continued to keep their software proprietary, so much so that most Tier Ones only reluctantly gave source code to their OEM customers. With consumers now demanding the same app based experience their car that they have on their mobile phones and tablets OEMs have turned to open source software to make up the gap. How did the ultra-competitive world of car manufacturers come to together to embrace Automotive Grade Linux and grow a community where Tier One suppliers, OEMs, and hobbyists can come together and build software for your next car? Walt reviews the challenges that were overcome, where we stand today, and what needs to be done to continue to grow the open source automotive community.

Linux enclaves have historically suffered from an excess of complexity. In RISC-V the necessary security primitives are built into the hardware. What is missing is a simple and robust open standard API that system architects and application developers can use without requiring in-depth security knowledge. In this presentation, Cesare Garlati - Founder of Hex Five Security and long time member of the RISC-V Foundation – and Dr. Sandro Pinto of the University of Minho will introduce the concept of a multi zone enclave for Linux and its underlying zero-trust computing model. Garlati and Pinto will present the implementation of the free and open multi zone API as a proposed standard for adoption in the RISC-V community and beyond. The multi zone API is like Docker at the chip level: it presents a minimalist API structure suitable for a thin, formally verifiable micro kernel, inter-zone secure communications, interrupt mapping, and trap & emulation for secure execution of micro-services.

Connected systems need strong security implementations to protect data, networks and the user experience. Many traditional products are becoming connected to provide end users with greater convenience and peace of mind. However, security is not “free”: it takes code space to store routines, energy to perform cryptographic calculations (impacting the battery life of a sleepy node) and computation time (which can adversely impact the user experience). This session surveys the impact of common cryptographic operations on code size, energy usage and computation time, using the test case of a battery-powered wireless sleepy node. This data-driven approach enables developers to make informed choices when designing a secure system. Evaluated operations include: • Symmetric encryption and decryption using AES technology • Random number generation • Key exchange using ECDHE technology • Secure boot (hash calculation and public key signature verification) • Encrypted firmware updates

Today’s microcontrollers designed for the IoT may come pre-loaded with a range of firmware from multiple vendors. While TrustZone for Armv8-M helps the protection of the device from hackers and untrusted parties, there are some cases where a fragmented supply chain can cause a higher risk of leaking trade secrets for firmware vendors. In these instances, devices need additional IP protection capabilities. These new capabilities bring changes to the processor's debug features, memory protection architecture and system-level security features. This presentation explains the background of these requirements, and how new features in the Armv8.1-M architecture can help chip vendors to deliver a solution to these challenges. For example, demonstrating how the Unprivileged Debug Extension (UDE) feature in Armv8.1-M restricts debug visibility to a specific software partition. To utilize UDE, debug tools and software require some adaptations and the devices need debug authentication support.

Today’s embedded designs must address a range of challenges, least of which is the embedded protections built into the system. The MCU-Based Alexa voice assistant solution is poised to enable the vision of "Voice Everywhere" to appease the demands of the digitizing world. The system solution addresses the challenges of voice capture, wake word recognition and cloud connectivity for Amazon Voice Services. The value of the intellectual property and services provided by the voice assistant is an attractive target for all ranges of cyber-attackers. This session will analyze the system level security protections inherent in this solution. The sensitive data handled by the system will be identified and the chip level protection mechanisms will be explained. The methods employed by the solution can be used for all types of embedded systems and improve the consumer trust. Join this session to explore the solution grade security available out-of-the-box for embedded designs.

Almost every microcontroller features firmware readout protection. It aims at securing the code, algorithms, and cryptographic keys against unauthorized access. Despite datasheets are promising strong security, our research shows that this is often far from being true. In this talk we want to shed light onto the "how?" we approach the security testing of such protection mechanisms. We will present and analyze several conceptual issues of state-of-the-art systems. While some concepts deliver a high level of security, others can be broken with low effort and almost no cost or complexity. In a practical demonstration, a selection of the presented attacks against readout protection will be shown live on stage.

FPGA implementations need special security means as cryptographic algorithms are particularly vulnerable against side-channel attacks. Other algorithms often encapsulate valuable IP that are not meant for public display so that reverse engineering supported by side-channel attacks can turn out to be a big problem. Using partial reconfiguration, the effort needed by the attacker can be increased remarkably. Thus, during the design synthesis, a multitude of functionally equivalent logic variants for the IP to be protected, are generated and stored in partial bitfiles. At runtime, those can be chosen by a controller and placed. The attacker cannot easily distinguish which variant is active during the process of the side channel measurement resulting in an increased overall effort. Therefore, Mixed Mode is developing a tool-based workflow that creates partial bitfiles automatically as part of the research project SecRec. Its configuration is done directly by annotations in the source code.

Slowly, as consumers replace or upgrade their electronic devices, USB Type-C is taking over the ports on just about everything. Not only is it becoming the defacto port, it’s becoming the only port type on may devices. Going away from laptops are a multitude of video ports (VGA, HMDI, Mini HDMI, DisplayPort, Thunderbolt, etc.) – never the right one when needed – but also charging, audio and any other interface. The USB Type-C is an extremely versatile connector port system. It is also unique from a power point of view. Not only can it source or sink power, it can provide different voltages at different power levels. No longer are we restricted to 5 V and a few watts. Now devices can negotiate their power requirements up to 100 W (20 V @ 5 A) if available. This session gives an overview of the USB Type-C power subsystem from source to sink including the type of power converters that can be used as well as protection and filtering devices required for a successful implementation.

Do you know designs which have a massive number of capacitors at the backside of FPGAs/microcontrollers? Sometimes the statement “the more, the better” is not right due to external components which can cause errors. The supply is the backbone of a good working electronic and should be understood as well as the signal lines. This lecture gives novel insights in the power supply design up to 6 GHz. With the concept of pairing several cheap and space-friendly blocking elements , it is possible to obtain an always working design. After this lecture, the visitor will know how to design state of the art power supplies for high-speed controllers. Not only is a lot of space saved but now the circuit will reduce the amount of radiated emission dramatically. The question whether buried capacitors are needed will be solved, as well as how to connect external components. Additionally, the origin of ground noise in case of supply design mistakes with VIA’s will be presented.

Data sheets can be confusing, especially when it comes to understanding power consumption. There is no standard method for conveying power consumption parameters in data sheets. In addition, many other factors must be considered that may not be adequately covered in a data sheet, such as wakeup times, radio transition times, peripheral activity, and transmit (TX) and receive (RX) times. The software stacks can also have an impact, and the efficiency can vary among vendors as well. This session will explore critical items to consider beyond the data sheet and will look at real-world calculators developed to benchmark battery life for IoT applications using Zigbee, Bluetooth Low Energy and Bluetooth mesh protocols. The session will discuss how to evaluate a wide range of data sheet specifications for wireless devices: • Active, RX, TX and sleep mode • Wakeup times • RX/TX transitions • Duty cycle • Application usage (e.g., wireless sensors) • Actual sleep current based on software stacks

Many electronic systems are being designed for world-wide operation. Power supplies capable of universal voltage range i.e. 85 V to 264 V are employed for this purpose. However, several regions around the world present design challenges due to line voltages frequently making significant excursions, up to 50 % above nominal voltages. Systems operating in Industrial environment also need to address surges from Electrical Fast Transients (EFT). Collectively, these scenarios create the situation of “Dirty-Power” at the input of power supplies. Creating robust designs to overcome this situation will require multiple techniques, including use of specially created surge-suppression devices to ensure failsafe operation. This presentation examines the design challenges and presents practical techniques and new technologies created to address this challenge.

Electronics, and specially, microcontrollers have taken over the automobile. The power source in a vehicle can vary far from the nominal 12 V battery. With cold crank starts the voltage can drop to as low as 3V. Disconnect the battery while the alternator is running and the resulting ‘load dump’ takes the voltage to near 90 V. Jump starts can be up to 24 V. Sometimes the battery is connected backwards by accident. Add to this +150/-220 V spikes from the ignition system not to mention +/- 25 kV ESD spikes. Can your power converter design deliver clean power to the microprocessor and its circuits? This session reviews the hazards which are clearly defined in standards and the various possible solutions for clean regulated power and transient protection in vehicles.

Reviewing specifications is an essential activity in safety projects in order to detect inconsistencies, ambiguities, and wrong requirements. It is also considered boring, difficult, and time-consuming. The challenge in detecting issues with requirements is they are mostly written in natural language and the tools used by teams for this purpose are generally only composed of a spell checker.

Multicore platforms exist for a long time but are not yet used for safety critical applications due to the certification aspect in aerospace, defense, automotive, railways, etc. Proving the safety and the determinism of the final application is a tough task. But applications require more computation power. The only path is to go to multicore platforms. SCADE is the industry-leading solution for designing safety critical embedded software and is used in numerous projects at the highest certification levels. Users produced millions of auto-generated lines of code while reducing cost of development by 40%. SCADE offers support for multicore platforms. The solution preserves the semantics of the application and is independent from the final platform as specific constraints to fulfill are produced with the code. The application partitioning is independent from the model.The same model can reuse without any changes even legacy ones. This solution was tested with different platform providers.

The DevOps (Development Operations) movement is sweeping the software development world but is the hype justified, is it all about automation and shortening feedback times and can it benefit those developing for medical devices and rail systems as much as those building e-commerce websites. This talk looks at the benefits, overheads and considerations associated with implementation of DevOps processes for build automation, release automation and compliance when applied to more traditional safety-critical or security-critical embedded software development.

Open source software is ubiquitous in embedded computing. Whether you are using the Linux or Zephyr operating system, open source machine learning components, or any other form of community based software, its important to understand the basic guidelines and principles for developing and managing open source software. This presentation will use multiple actual industry examples to demonstrate practical tips and tricks for open source software development. Topics include developing an open source policy, understanding the basics of licensing open source software, how to update promptly, using a binary repo manager, how to particpate in the community and upstream software, how to use the proper build tools, tips for how and when to fork, and other practical examples. With the right framework and understanding, open source development for embedded systems can be more efficient, and less risky and error prone for the developer and the organization.

Finite State Machines (FSM) are quite useful in reactive systems when there are many inherent states. However, number of states and code size increases exponentially with these machines (Mealy and Moore) and hierarchical form of state machines is needed to reduce complexity. Our model is an extended version of state pattern in Gang of Four for hierarchical (nested) states with entry() and exit() actions. We propose a simple yet powerful Hierarchical Finite State Machine (HFSM) which is scalable, efficient and easy to debug. We exploit the polymorphism and inheritance using C++03. Although we used proposed implementation on a real time embedded project, it is not restricted to embedded world, can be used on any platform.

In C and C++, it can be very convenient to allocate and de-allocate blocks of memory as and when needed. This is certainly standard practice in both languages and almost unavoidable in C++. However, the handling of such dynamic memory can be problematic and inefficient. For desktop applications, where memory is freely available, these difficulties can be ignored. For embedded - generally real time - applications, ignoring the issues is not an option. Dynamic memory allocation tends to be non-deterministic; the time taken to allocate memory may not be predictable and the memory pool may become fragmented, resulting in unexpected allocation failures. In this session the problems will be outlined in detail and an approach to deterministic dynamic memory allocation detailed.

Proof of functional safety requires the collection of structural coverage information to confirm that the structural coverage is appropriate for the software level. A new trace-based observation methodology provides the key means to gain a non-intrusive insight into the execution of production code for multi-core SoCs. To cope with the enormous bandwidth of the produced trace data we have automated the analysis of the trace data on-the-fly. We enable the automated detection of raising timing constraints and the certification of test coverage. Most importantly, these structural tests are executed on the basis of the production code without the need for software instrumentation. The presentation provides an overview of the applicable functional safety standards, explains the advantages of executing structural tests even at higher test levels, and gives practical hints for hardware and software architecture considerations for providing best observability for executing structural tests.

Security is an increasing concern for developers of many small embedded applications such as IoT Edge devices. Unfortunately the choice of tools suitable for testing security on such systems is limited. This is quite different to web-based, desktop and even embedded Linux application developers who are able to select security tools from a wide range of commercial and open-source providers, such as those included in the popular Kali Linux distribution. This paper considers if it is practical to use free or open-source tools to test security vulnerabilities of a small embedded system, based on an Arm Cortex-M MCU running a bare-metal application or a Real-Time Operating System (RTOS). It looks at readily available tools for threat modeling, static analysis, software reverse engineering and fuzz testing to determine how much work is required to use them on a project and whether it is worth the effort.

Unit testing is a popular testing technique, widespread in both enterprise IT and embedded/safety-critical worlds. For enterprise IT, unit testing is considered a good practice and is frequently followed as an element of test-driven development. In the safety-critical world, there are many standards (e.g. ISO 26262, IEC 61508) that either directly or indirectly mandate unit testing. But unit testing is very time-consuming, and teams are looking for strategies to optimize their efforts, especially in the safety-critical space, where demonstration of test coverage is required for certification. In this presentation, we share the results of our research regarding the use of advanced code analysis algorithms for augmenting the process of unit test creation. Key to the discussion is automatic discovery of the inputs and responses from mocked components that maximize code coverage, and automatically generating test cases to optimize test creation time.

Taking advantage of multi-core processors for safety-critical real-time systems significantly increases their complexity and probability for complex transient faults, turning debugging into a time- and cost-intensive nightmare. While debuggers fail to reproduce intermittent bugs, tracing, especially hardware tracing, is the choice to not interfere with the program execution, permitting a deep insight into the system’s behavior. However, current tools often fail to track down the bugs’ root causes, due to limited trace buffer sizes and trigger mechanisms. In this presentation, a novel tool is presented, overcoming these issues by processing the hardware-trace in real-time, providing complex triggers and variable monitoring scopes, followed by post-mortem analysis. It is demonstrated on an example system, having tight end-to-end timing constraints. The approach permits preventive monitoring even before the program fails and allows mastering the evolving complexity in embedded development.

The complexity of applications is always increasing and to handle the increased workload, multicore devices are becoming more popular. The combination of different architectures, for example Arm Cortex-M/R/A cores and RISC-V RV32/RV64 cores is becoming a more common practice in order to get better performance. These scenarios can range from two cores, up to tens or even hundreds of cores! By using multicore devices it’s possible to load balance, take advantage of the different strengths of the different architectures, and you might even lower the product cost by using one multicore device rather than multiple devices. But how you can debug all those cores in an efficient way? This seminar will explore the challenges on how to simultaneously debug two or more identical cores ((SMP), and multiple cores with different architectures (AMP), all in one single debug probe interface. This session will guide you to understand and master the deployment of a multicore application.

This presentation shows the usage of debugger for the automated software test of embedded systems to fulfil the requirements from standards (e.g. IEC 61508, ISO 26262). It focuses on the integration of different debug systems (e.g. iSYSTEM, Lauterbach) into the framework for automated software tests with HIL systems for embedded systems. Based on project experience the possibilities and advantages of the usage of debugger in the automated software test is shown. The measurement of the code coverage of the test without changing the code of the embedded system is a big advantage of this approach. The possibility to increase the test coverage by accessing values inside the software of the embedded system and so the enlargement of the usage of the HIL test from the pure black box test to the range from module test to system test (grey box test) is a big advantage. In summary the possibility and the advantages of the usage of debugger for the automated software test are be shown.

With Deep Learning algorithmic advances outpacing hardware advances, How do you ensure that algorithms of tomorrow are a good fit for existing AI chips under development ? ,However, most of these AI chips are being designed for the AI algorithms of today, Given the rate and the magnitude of algorithm evolution, many of AI chip designs may become obsolete even before their commercial releases. Algorithms of tomorrow demands overhaul of architecture,memory/data resources and capabilities. Dream architecture for Inference has to redefine some fundamental chip techniques that rewrite the rules in computing and delivers breakthrough AI acceleration and flexible compute capability than server-class CPUs and versatile than GPUs/ASICs to support breadth of applications,dynamic workloads. Author will discuss how these industry challenges can be addressed at various levels of hardware and software design using VERSAl AI Core which leapfrogs CPU/GPU/FPGAs and being industry's first ACAP's device.

Machine Learning is moving to On-Device or Edge for reasons of latency, power, security. ML Algorithms that were once designed to work on high end GPUs & not on embedded systems. This brings in new sets of challenges in designing ML solutions for embedded involving small memory footprints, limited to no float point operations, rich instruction set of fixed-point operations, proprietary software tool chains, libraries. This paper talks about addressing these ML challenges for Embedded Systems and challenges required to support wide range of ML frameworks, network types and layers, performance, accuracy loss. Our proposed solution consists of: • converting pre-trained floating-point network models of some of the popular ML frameworks into a common proprietary model format • custom quantization techniques to quantize model • selection of most optimum library function, kernel fusion, kernel rejection • tiling and DMA management of data • generate highly optimized platform specific executable

Currently, AI applications demands for large models with huge MAC operations. In order to deploy such applications with a practical performance, powerful hardware is often needed, which will also consume more power. This paper proposes a new FPGA design using low bit quantization technique which uses 4 bit for both weights and activations, but can still keep accuracy of original neural network. Such low bit CNN design can achieve significant performance boosting and higher power efficiency. Our paper will use OpenPose algorithm as the demonstration for AI application, which is popular in pedestrain detection and the model is large enough. With our low bit CNN design, and optimized post-processing for OpenPose algorithm, we can see more smooth pedestrain detection application compared to original design.

We have seen transformational waves in computing over the last few decades, and we believe AI is a key one - already ongoing. It has significant impact in many research and industrial areas enabling users to get more actionable insight from data.   The data often comes from devices. - such as cameras, sensors and more. Some data processing using AI technologies happens in the devices already.   Gateways and the datacenter are the places where more analysis of the data is done and prepared using AI. A solution cannot be isolated to the device or the data center level but has to be designed end to end. In this presentation we give an overview of respective technology for Artificial Intelligence, with a special focus on how to enable successful development of end to end AI solutions. We will look into how to do this with the technology used for general computing today as well as with specific technology for AI workloads. This will also be illustrated with practical customer examples.

Executing neural networks on embedded processors like Cortex-M4 presents several challenges: limited memory, low computing power, no operating system, etc. In addition, an efficient workflow for porting a neural network from e.g. Tensorflow or Keras to an embedded target is needed. Currently, several frameworks that offer such a workflow are available. This paper examines four currently available solutions and compares them: Google: tfLite, ARM: CMSIS-NN, ST: Cubex-AI, Renesas: e-Ai. The frameworks differ considerably in terms of workflow, features and performance. Depending on the application, one framework is better suited than another. Typically, neural networks that are ported to embedded platforms with these frameworks are static. This means that once they are integrated into the firmware, they can no longer be adapted. In the context of this work, possibilities of unsupervised learning on the target was investigated and is discussed in the presentation.

They have been around for a while: Devices combining multiple CPUs, GPUs, co-processors and FPGA fabric on a single chip or module. All these components need programming. And all these are reconfigurable: Their function can be altered in various ways at runtime. This presentation will explain how to do that in practical examples. Free yourself from the limits of the classic boot sequence where the bootloader configures the pins and programs the FPGA and drowns the system configuration in virtual concrete. In small steps, make your system adapt itself, allowing access to a broader range of applications while also reducing the maintenance on board and device support. This talk will focus on the tools and infrastructure available today to actually put this technology to work. We'll see practical applications of how we can use Linux' Devicetree support to make the system adapt itself at runtime and how one could deal with add-on boards.

RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration. The RISC-V foundation now has close to 300 member companies and universities, and growing. This talk will focus on the state of the technology for RISC-V. We will discuss the latest developments in the RISC-V foundation regarding technology development, discuss some of the new communites like openHW Group that are dedicated to creating high quality open source RISC-V implementations for the masses. We will discuss industry adoption of RISC-V, using actual examples of how to incorporate RISC-V into a corporate design flow. We will discuss what is being done to manage hardware and software fragmentation in this growing community, and the state of the RISC-V ecosystem. We will show examples of how to innovate by using the powerful instruction extension capability of the ISA.

Secure Element (SE) in SoC sees an increasing adoption in industry. Most secure solutions in IoT devices are bound to the SE because it provides strong cryptographic functions and physical protection. Though SE-in-SoC provides strong proven isolation for software programs, it also brings more design complexity and higher cost to PCB board building. More, SE-in-SoC may still have security concerns, such as malware installation and user impersonation. In this work, we employ TEE, a hardware-backed security technique, for protecting SE-in-SoC and RISC-V. In particular, we construct various enclaves for isolating applications and manipulating the SE, with the inherently-secure features provided by RISC-V. Using hardware and software co-design, the solution ensures trusted execution and secure communication among applications. The security of SE is further protected by enforcing the SE to be controlled by a trusted enclave and making the RISC-V core resilient to side-channel attacks.

Many emerging high performance embedded SoCs are based on accelerators ... This presents the unique problem with multiple peer processes and achieving the highest Performance/Power ... We will discuss a fitting architecture, and over a dozen techniques for increasing Performance/Power by using Power Management ... The examples will center around the Xilinx Zynq UltraScale+ MPSoC and Versal ACAP parts.

With increasing signal processing requirements in various types of embedded systems, we have seen a number of new chips on the market that combine both a digital signal processor (DSP) and a general purpose processor to address the processing demands. While this suits high-performance devices where silicon area and power are less of a concern, such devices could be difficult to program and can have limitations. To address the challenge, Arm has been working on technologies that boost the signal processing and machine learning capabilities for future embedded processors. In this presentation, we will look at how Arm Helium technology compares to features found on traditional DSPs, and some of the fundamental differences between VLIW (Very Long Instruction Word) architecture and the Helium approach to the processor's pipeline design. We will also look into how the processing requirements affect the processor's level-one memory system design and system design considerations.

Adoption of new interfaces on next generation semiconductor devices requires redesign of physical interfaces, link layers and processor core connectivity. These architecture updates often require strategic forecasts beyond current market insight and as a result long development cycles and non-optimal devices. Resolutions to these issues have been seen in current and next generation programmable devices. Bridging between interfaces with FPGAs or fixed function ASICs have traditionally been an early crutch for legacy SoCs adoption. Looking forward, programmable SoCs provide not only a path for early interface adoption, but the ability to provide only the necessary connectivity to the processor core. This allows for real time development of an SoC that is customized for a particular use case. Use cases and unique programmable solutions will be explored for the purpose of this presentation.

5G will have a huge impact on the automotive industry overall, connecting vehicles to the smart city of the future and paving the road to autonomous driving. As we did in 3G and 4G Qualcomm played a key role in all parts of 5G, e.g. Qualcomm began 5G R&D in 2006. 5G will enable new mission critical services with ultra-reliable/available, low latency links for road safety and autonomous driving.

Development of 5G products is accelerating with the first device and network deployments in 2019. 5G New Radio (NR) technology introduces a flexible architecture that will enable the ultra-fast, low-latency communications needed for next-generation mobile broadband networks and applications such as connected autonomous cars, smart buildings and communities, digital health care and industrial IoT. The flexibility of the 5G NR standard will make design and test more complex. Engineers developing 5G enabling technologies and connected devices need a solid understanding of the fundamental concepts behind the 5G NR specification as well as standard compliant functions and reference examples. In this paper, we introduce the key 5G physical layer technologies and concepts. You will learn about the structure of 5G waveforms; how the waveforms are constructed, modulated, and processed; beam management in massive MIMO systems; and methods for simulating and measuring link-level performance.

Private LTE/5G networks have key benefits and applicability well aligned with enterprise IoT applications including increased coverage, carrier grade security/privacy, customizable QoS, higher reliability, high throughput and low latency to edge services versus other wireless standards. This technology also has the capacity to support video and AI without incurring cost/bit models from local mobile network operators. This presentation discusses private LTE/5G cellular network architectures, benefits of this technology, applicability to future IoT product applications, and results of initial Lab evaluations of such networks. In particular,results of our current technical evaluations for specific private and hybrid private/public network topologies including measured network latency, throughput, and QoS performance metrics will be shared.

The goal of Industrie 4.0 is to significantly improve the flexibility and efficiency of production systems. Generally, Industrie 4.0 delivers seamless vertical and horizontal integration across the entire value chain and all layers of the automation process. Connectivity is a key to implement Industrie 4.0. Wireless communication, and in particular 5G, is an important way of providing powerful and pervasive communication between machines, people and objects. One of the main differences between 5G and previous generations of cellular networks lies in 5G’s strong focus on machine-type communication and the Internet of Things (IoT). 5G networks will achieve manufacturing flexibility on the factory floor, support a wide variety of sensors, devices, machines, robots, actuators, and terminals. The capabilities of 5G thus extend in communication with unprecedented reliability and very low latencies, and also massive IoT connectivity. 5G’s basic potential is in connected industries, in particular the manufacturing and process industries. In this presentation, I will provide an overview of 5G’s basic potential for manufacturing industry, and describes the most relevant use cases and the corresponding 5G functions and service requirements. Furthermore, I'll introduce to some of the main building blocks of 5G and certain major challenges ICT and OT industry are working on to be resolved with next releases of 3GPP. Further this presentation examines how the 3GPP-defined 5G architecture will impact industry, especially process and discrete manufacturing. In particular the presentation considers key aspects and service attributes that can help to highlight the differences between deployment scenarios for 3GPP-defined 5G nonpublic networks. In contrast to a network that offers mobile network services to the general public, a 5G non-public network (NPN, also called private or campus network) provides 5G network services to a clearly defined user organization or group of organizations. A number of network implementation options for NPNs based on 3GPP specifications will be described. These range from completely self-contained standalone NPNs that have no connection to the public network, to NPNs that are hosted entirely by public network operators. The main implementation questions will be addressed.

While Wi-Fi provides some level of consumer ease of use and security for IoT devices, network technologies like 5G, NB-IoT and LTE-M are the next step. With cellular connectivity, products can work straight out of the box by connecting automatically to the local network. To create network agnostic and secure devices, manufacturers need to adopt a security-by-design mindset, protecting both their products and their customers’ data from the silicon up. This presentation describes the current IoT landscape. It explains how the evolution from embedded SIM (eSIM) to integrated SIM (iSIM) can increase your IoT product’s total available market and improve its security. Finally, it gives examples of integrated security IP solutions that help protect IoT product data, from silicon to remote provisioning.

Following up on last year’s session, “Radio Scheduling in Dynamic Multiprotocol Applications,” we are now seeing real-world IoT products making use of DMP functionality to open up new use cases. This session will summarize new and emerging use cases enabled by DMP technology. In addition, the session will detail how different standards organizations are reciprocating with multiprotocol use cases. Historically standards organizations like the Thread Group, the Zigbee Alliance and the Bluetooth SIG viewed each other as competitors seeking dominance in the IoT market. To a certain extent, this competition is still occurring. However, it has become clear that no single standard will dominate the market in the near term. This has led to movements among these standards groups to aid implementers designing connectivity solutions that support more than a single protocol. For device manufacturers, this trend still leaves some hard decisions, but life in the IoT design world is becoming easier.

With each new IEEE 802.11 Wi-Fi standard, the data throughput has been improved to deal with the ever-increasing demand from new applications requiring higher data throughput. The new IEEE 802.11ax standard continues this trend with higher throughput alongside new features that allows it to perform in dense environments in an efficient and robust manner, improving performance for the user. However, for low power, low data rate, battery operated applications, Wi-Fi has traditionally has not been used as much as other wireless standards as it is seen as less power efficient. As well as improving data rates and robustness, IEEE 802.11ax is designed to address this problem with a range of new features. During this session we will discuss the new features and explain why IEEE 802.11ax 20 MHz option is the perfect choice for the IoT / wearables / low power Wi-Fi markets and should be looked at rather than the older IEEE 802.11n standard.

NFC technology exists for around two decades. Some of its use cases like payment and access control have completely changed these industries and had a significant impact on our lives. With NFC evolving further, we are set to explore and move into new horizons; to do a part of what an MCU does. This doesn’t mean competing with MCU or replacing it but there are sensor use cases where an MCU is an over kill and customers pay the price. We propose to fill this gap with the latest and greatest NFC technology. With secure NFC chip which has an I2C master interface, one can create a bridge between the sensors in a device and a wireless outer world. A use case where you only get the data when you need it in a single shot and transfer to the cloud or use it as a measurement in the field. On top, there is another great quality that NFC offers. It can harvest energy from the external device in its vicinity and power up a complete circuit including the sensor! That’s where the whole game changes.

DECT is one of ETSI’s first and most successful technologies. As the technology evolves to meet the requirements of the 5G application landscape, this paper will show how DECT has re-defined itself and continues to attract new applications, innovators and brand names with a high professional demand for wireless in their portfolios Did you know that DECT figures heavily in pretty much every walk of life? What will surprise many however, is the fact that the applications using DECT have one thing in common: They have an overriding need to be utterly reliable. They carry the demands of professional applications like Emergency services, Flight Control centres, Power Plants, Airport ground staff, Hospitals, Campuses and the whole area of Programme Making and Special Events (PMSE). In the home, operators are also making use of the DECT radio found in almost every European home gateway for DECT based voice and low powered Smart Home services. The current requirements of many of these applications are in line with the demands of 5G. This ties in nicely with how DECT and ULE are evolving to become a 5G technology for the 5G key use case scenarios URLLC (Ultra Reliable Low Latency communications) and mMTC (massive Machine type communications). Becoming a 5G approved technology will imply significantly enhancing the specification, allowing DECT to go well beyond its current parameters, while leveraging the installed base by being backward compatible. Voice in different forms, as well as smart home and building will remain key markets. By lowering latency, improving range, bandwidth, and reliability DECT for 5G will address a range of new industry verticals that require its unique offering for mission critical applications. This application diversification will also be supported by its openD API for wireless application development based on DECT ad ULE. This paper will outline how DECT already addresses many mission critical markets and how it will underscore this uniqueness to become a 5G technology that will complement other 5G technologies to bring best quality wireless for demanding environments.

The new Time-Sensitive Network (TSN) standard will create new opportunities to combine critical real-time (RT) traffic with uncritical user data from conventional Ethernet networks. The main strings of these networks will operate at 1 Gbit/s. TSN is still cable-based, which makes it inflexible for mobile applications. For wireless TSN-connectivity, radio-frequency (RF) based technologies like Wi-Fi are no option due to their insufficient latency and bandwidth. However, it was shown that Li-Fi is able to meet RT requirements with high bandwidth. This work introduces a two-port Li-Fi TSN node for 1 Gbit/s full-duplex wireless RT communications. The node includes a processing unit, which makes it possible to connect to external controllers, run higher level protocols like OPC UA or attach non-TSN devices. The work shows how to program embedded designs that make use of Li-Fi and TSN. Bandwidth and latency measurements within a TSN network prove the functionality with mobile devices.

Complex embedded system software assembly is undergoing dramatic change. Applications are increasingly being delivered integrated and packaged with their own custom OS instance. This trend started with IT systems leveraging virtual machines and containers and has now come to the embedded system arena. With the huge amount of software landing in discrete multicore embedded systems having diverse core values and needs, one OS instance is no longer able to provide an optimal operating environment for the breadth of applications that must be run. Applications may be developed for a particular OS, or continually evolving or frozen such as with open-source and certified systems respectively, or may simply come from multiple sources and thus need to be partitioned for licensing or release cadence reasons. We will explore new heterogeneous distributed system architectures targeting multicore SoC embedded systems and what that means when creating, capturing embedded software value.

Virtualization is already a key-enabling technology for mixed-criticality embedded systems. Open-source hypervisors such as KVM or Xen were not originally tailored for embedded constraints and real-time requirements, and depend on Linux, resulting in large TCBs and wide attack-surfaces. Furthermore, they do not address the numerous microarchitectural contention points and side-channels that have been shown to break true VM isolation. Bao is a lightweight, open-source embedded hypervisor which aims at providing strong (microarchitectural) isolation and real-time guarantees. Similarly to Jailhouse, it is a partitioning hypervisor leveraging hardware virtualization support; unlike Jailhouse, it is completely self-sufficient, not depending on Linux. Currently supporting ARMv8 and RISC-V, Bao was developed from scratch to provide a minimal clean-slate and industry-grade solution and engage both academia and industry to tackle the challenges of modern automotive and industrial systems.

When developing embedded systems, it is common to have mixed-criticality requirements: one application is critical, and typically comes with real-time requirements, while the other is far less critical and it is often based on Linux. Xen on ARM enables static partitioning configurations with Dom0-less, a recent feature to boot multiple domains in parallel directly from the hypervisor. IRQ latency and real-time are critical enablers, but real-time cannot be guaranteed when the underlying cache is shared across CPU cores: cache interference degrades IRQ latency, causing real-time applications to lose deadlines even on native. This talk will go into details on the issues caused by cache interference on Arm CPU cores; it will introduce Xen Cache Coloring, a new technology to zero cache interference effects between domains. We will demonstrate applications retaining their expected level of IRQ latency under severe stress conditions.

Using virtualization in multi-core based embedded systems becoming more popular due to the benefit of system consolidation resulting in cost and BOM reduction. However, the process of designing and running applications on top of an embedded hypervisor might not be straight-forward. This presentation describes the main considerations for deploying embedded hypervisor in systems with security, safety, and real-time requirements. Spatial isolations between guests, temporal isolations between guests and host, CPU and priority scheduling, isolation and classifications of safety and non-safety components are some of the topics covered to help understanding the common aspects, challenges, and pitfalls of designing systems with embedded hypervisor. Furthermore, the presentation will share some test and measurement techniques which can help system designers having better overview on the overheads of running multiple OSes and applications in a virtualized environment.

With the move to consolidation and the growth on connectivity to the cloud, how can a system obtain the new functionality all while maintaining the safety needs? This has led to the rise of mixed safety-criticality systems on a single embedded device. This session will explain the use of OpenAMP to solve the requirement of mixing safe and non-safe worlds on a single device.

Our ability to rely on total privacy of communication is under threat, and will likely disappear in the future. Law enforcement for too long have been thwarted by encryption protocols that are seemingly impossible to circumvent - leaving criminals able to communicate across networks without fear of interception. Many feel that it is not possible to resolve this issue, as cryptography is maths, and governments cannot change this fact - but this is not the whole story. In this presentation, Kris Chaplin will discuss how the needs of law enforcement to intercept criminal communications could be implemented in a cryptographically 'safe' way. Secure communications will need to be changed, probably forced by legislation, along with the free movement of packets on the internet. However if done properly, it could all work together without backdoors or overly-broad governmental access. One aspect is for sure - should this mechanism be implemented, the internet will never be the same again!

IoT is playing an increasing role in international infrastructure. If manipulated, they can bring catastrophe to smart cities, telcos, power plants, etc. Thus, ironclad cybersecurity that can protect against a variety of attacks & prevent the intrusion of unauthorized agents is paramount. Common security methods in use may seem adequate, but there are weak points in the processors. For ex., researchers demonstrated the danger & ease of attacks by compromising Siemens Simatic S7 PLCs (industrial hardware controllers used in power plants & production lines), seizing control of the devices to load various logic, change the activation/source codes, & introduce malicious programs—all inconspicuously. This presentation will use this example to talk about the flaws the processors controlling power plants & factory floors, explain how these flaws can be exploited to cause damage, & demonstrate how a cloud-to-flash approach can protect our critical infrastructure even if the PLC is hacked.

Differential Power Analysis (DPA) is a side-channel attack based on a statistical method of analyzing a device’s power consumption to identify data-dependent correlations. These correlations can be used to leak keying material without requiring an exploit of the underlying algorithms or protocols. This session will explain the concepts of side-channel attacks, simple power analysis (SPA) and differential power analysis and will also present results based on power measurements from an experimental side-channel attack. The primary takeaway is that DPA technology is available today even to hobbyists, thus presenting a security threat to many IoT devices. After a brief explanation of the math behind DPA and SPA, the session will focus on suitable countermeasures in hardware, software and system design. Hardware countermeasures are mostly left up to IC manufacturers to implement, and there are many other techniques developers and system architects can use to prevent side-channel attacks.

Software is typically written assuming the underlying hardware performs (roughly) as intended. But attackers can exploit that fundamental trust to completely break embedded systems. Attackers can use fault injection to bypass instruction execution - this super-power means that tasks such as validating a firmware signature can be easily broken. Embedded developers must be aware of these attacks, and how to write code that can resist them. This work covers important concepts on this topic, and introduces open-source (and freely available) libraries and tools that can help developers avoid these attacks. Several examples are pulled from real products that have been broken with fault attacks, along with several open-source libraries that are vulnerable to fault injection attacks. While this work only serves as an introduction, it sets a path forward that developers can follow to find more information and perform their own experiments with open-source tools.

Due to their computing power, quantum computers may have the disruptive potential to break various currently used encryption and authentication algorithms within the next 15 to 20 years. Once available, quantum would threaten currently used asymmetric algorithms such as RSA and elliptic curve cryptography (ECC). An approach that aims to replace RSA and ECC in next generation security protocols is post-quantum cryptography (PQC). In this presentation, we show the challenges of implementing PQC on embedded devices and smart cards. One important aspect is the protection of schemes against attacks like power analysis and fault injection and research on this topic is still in a very early stage. Moreover, we describe how existing cryptographic hardware on smart cards or embedded microcontrollers can be used to accelerate post-quantum cryptography.

RISC-V is being broadly adopted across many applications. It is still early in the ecosystem development, but adequate tools and infrastructure are available for development. This presentation will detail the development of a RISC-V based SoC which is incorporated into a storage controller. The development trade offs and decisions which were made will be shared. The ultimate block diagram of the SoC will be shown. In addition, the data path challenges that the RISC-V SoC solves will be explained.

Many IoT and hand-held devices rely on actuators, despite having limited energy – often a battery. These batteries preferably have a low cell count, with a voltage range of 2.4V – 4.3V for most devices, whether it’s for security, home automation, medical, or POS devices. Actuators in these devices often need only short-term motion, e.g. when adjusting a valve or dosing a medicament. However, limited power restricts both peak power and long-term energy consumption. Thus, energy efficiency is critical – even with a low duty cycle. The paper focuses on these challenges of driving a stepper motor with such low voltage, like a single Li-Ion cell or dual AA-Battery, and compares the practical aspects to driving a DC motor from these current sources. Measurements from an example setup show the limitations and deliver performance figures for the motor and driver combination. A topology with step up voltage regulator is compared to a solution with a motor wound for low voltage operation.

ECG measurement using galvanic coupled electrodes is an established method for monitoring cardiac activity in medicine. In some cases, the use of gel electrodes leads to skin irritations. In addition, the electrodes have to be connected to the ECG recorder via cable. Wearing the electrodes and cables is inconvenient for the patient and they can lead-off unnoticed during motion. There is also a psychological effect related to the wearing of medical devices, which can influence the diagnostic assay. The motivation is to improve the long-term application on patients by using a non-galvanic capacitive ECG measurement system completely integrated in a smart cloth. The developed measurement system consists of two circular sensors with active and passive shielding. A Pan-Tompkins algorithm for R-wave detection has also been implemented. First motion tests with an ergometer were successful. The results of the capacitive ECG measurements are comparable with those of the galvanic measurement.

N-Blocks is a modular open source low power embedded systems platform based on a “Lego”-style concept where computing, sensor, harvesting, and communication boards can be plugged together for particular embedded wireless node capabilities. Processors are used based on the ARM cortex-M series and communication capabilities include Bluetooth Low Energy, LoRa, WiFi, IEEE802.15.4/Zigbee and NB-IoT. Sensing capabilities include temperature, humidity, acceleration, light, VOC, CO2, air quality, and optical sensors. A complimentary open source graphical software tool using a flow based programming paradigm allows developers to programme nodes and build applications. N-blocks has been evaluated in a number of academic-industry pilot projects for use cases in environmental monitoring applications, smart building applications and health care applications. We have also compared N-blocks in terms of functionality and performance to other similar open source embedded systems platforms.

For operators of widely distributed, decentralized plants and machines in the field of conveyor technology, the plant locations are often remote and not quickly accessible. Personnel are often not on site. Maintenance in the event of machine breakdowns is particularly time-consuming, downtimes and costs are enormous. The lecture is dedicated to the application example of a predictive maintenance solution) using Fast Fourier Transformation (FFT). The method records and analyses the vibrations of rotating or vibrating components in order to determine wear and tear, loosening of mechanical connections or the penetration of foreign bodies. Recorded as signals by microphones or acceleration sensors, the signal transformation from the time to the frequency domain subsequently enables the mechanical evaluation of the condition. After this analysis, the current condition of the machine can be estimated on the basis of the recorded frequency spectrum and wear can be detected at an early stage.

Understanding the compilation process is crucial to generating the most efficient machine code from your source code. Compiler technology has not yet run it course, and new cutting-edge optimisations have made enormous execution and code size savings. This talk will survey some of my favorite optimisations: some are old, but highly effective, while others are virtually unknown outside of the tight knit community of compiler developers. All of them are, in my opinion, quite fascinating.

Architecture models serve as documentation of major architecture decisions and offer guidance for the planning of extensions to the software. Safety standards like ISO26262 require projects to develop an architecture model and to ensure that model and code are in sync. With increasing project complexity, the latter becomes difficult: changes to the code, e.g. during integration on a hardware platform, need to be reflected in the model. Without this feedback, the architectural model would no longer be a correct abstraction of the code. Manual checks of code/model discrepancies are time-consuming and incomplete. We introduce a workflow that uses static analysis tools to automate these checks. It automatically reports model deviations like missing dependencies and faulty activity diagrams, and handles different meta-models by using graph transformations. Examples from the automotive industry show how the checks improve model quality.

Many embedded solutions have to be compliant to regulatory requirements. For system conception it is required to know the achievable performance before the final SW-stack is completed to verify if the goal can be achieved with a certain module arrangement. Here we show methods how embedded SW-modules are characterized in performance, functionality, timing and resource consumption. This can in some way be compared like the characterization of a HW-module with all its performance and limits. The methods are shown with the use case of a flow meter SW stack running on the latest MSP430 high performance metering device series.

The proper way to manage software performance is to systematically plan for and predict the performance of the emerging software throughput the development process. This is important in embedded real-time systems where performance is an explicit, measurable requirement. Achieving performance goals is not something you want to think about towards the end of the software development process! Software Performance Engineering (SPE) is a comprehensive way of managing performance throughout the lifecycle, that includes many practical guidelines and principles for creating performant, scalable, and responsive software. This presentation will present a set of useful techniques, reinforced by industry examples that you can use to manage the performance of your software throughput the lifecycle.

While 85% of embedded designs use C and C++, these languages are notorious for allowing unsafe code practices that give hackers a way to attack. This talk shows exactly how to keep your internet-connected product safe by writing your code properly the first time. Well-proven tools and techniques can be used to augment any software design paradigm and to effectively hack-proof your code. Techniques include coding conventions, automatic run-time error checking, manual compile-time and run-time assertions, static analysis, and the most common mistakes to avoid.

Anomaly detection, the art of finding rare events or observations that differ from the norm, has many applications. Anomaly detection is becoming increasingly popular due to Internet of Things (IoT) devices, whereby lots of data is generated but where manual labeling is not always feasible. In this talk, you'll learn how a cloud-trained ML model deployed on an edge camera can be used to detect anomalous objects and uncharacteristic movements in video data.

Machine learning techniques have proven to be very effective for a wide range of image processing and classification tasks. While many embedded IoT systems deployed to date have leveraged connected cloud based resources for machine learning, there is a growing trend to implement this processing at the application edge for applications where bandwidth or latency are a constraint. Selecting the appropriate system components and tools to implement image processing at the edge; lowers the effort, time, and risk of implementing these designs.

With an increasing number of embedded systems becoming smart, new opportunities are opening up. Most of these new smart embedded solutions rely on machine vision (software) to perceive their environment and base their decisions on the information contained within the acquired image data. The complexity hiding behind choosing the “right” machine vision software to be integrated into smart embedded devices is, therefore, not to be underestimated. The technical paper and corresponding presentation will look into different aspects that play an important role from an economic point of view, paying special attention to the currently observable developments in the embedded market. Subsequently, it will present technological factors to be considered when opting for a machine vision software: the software’s feature set itself, connectivity and compatibility. To conclude an outlook on how the embedded vision market might develop will be presented.

Many embedded systems nowadays make use of image sensors to solve a high variety of problems. Those are connected directly via MIPI CSI-2 and provide raw image data to the embedded platform. Before running algorithms to solve the actual problem, the image data needs to be pre-processed.This is done by the Image Signal Processor of the platform’s SoC. The capabilities of available ISPs for different SoCs highly varies from each other. Another aspect is that missing image processing features needs to be implemented in software, which then can be executed on either GPU or CPU. Applying any image processing to either of those would block therefore valuable resources. The technical paper and corresponding presentation analyzes different ISPs, their capabilities and their interfaces. With help of performance and resource measurements those will be compared and how the system can benefit from Alvium camera series is shown.

Embedded vision and inferencing is seeing rapid momentum as advances in GPU technology have put powerful compute hardware in the hands of machine learning developers. The landscape of SDKs, APIs and file formats for accelerating inferencing and vision applications continues to evolve. Low-level compute APIs, such as OpenCL, Vulkan from The Khronos Group and CUDA are being used to accelerate inferencing engines such as OpenVX, CoreML, NNAPI and TensorRT, being fed by Neural Network file formats such as NNEF and ONNX.  Some of these APIs, like OpenCV, are vision-specific, while others, like OpenCL, are general-purpose.  Some engines, like CoreML and TensorRT, are supplier-specific, while others such as OpenVX are open standards that any supplier can adopt.  This session addresses the various open standard and proprietary APIs, discusses the benefits and tradeoffs and helps attendees decide which ones they should use for their embedded vision projects.

Creating embedded products is often a struggle of compromises. The GUI Designers cannot realize their wanted UI, because the hardware and framework has its’ limits, and the GUI Developers are then stuck with a series of tough choices, all of which seem to give half-decent results. Creating successful products requires teamwork between multiple disciplines, which consists of different skill sets and different people. Often this combination of disciplines becomes a clash of skill sets, interests and personalities, ultimately leading to failed communication and misunderstandings, failing to reach the common goal – the successful product. Through a decade’s experience of designing and implementing embedded GUI solutions for a broad range of industries, which have proved to be an integral part of a successful project. There is hard focus on skill sets in the industry, but we will argue that communication and teamwork is just as important, when delivering a world class embedded product.

Today’s aircraft are increasingly digital, featuring automation, artificial intelligence, electrification and other advanced technologies. The trend toward digitalization is revolutionizing the cockpit, which now includes new controls, displays and touchscreens that enable pilots to interact with innovative technology systems. Optimizing these human machine interfaces is an incredibly complex task, bringing logic and science together with intangible factors including human vision and comfort. The good news? Powerful new simulation capabilities are making it possible to take virtual cockpit models for a “test flight” — well before any investments are made in physical testing and prototypes. By optimizing human-machine interfaces in a risk-free, virtual setting, aerospace manufacturers can be first to market, while still meeting their profitability goals and industry safety standards. We will demonstrate this concept in the presentation.

The fast pace of innovation in automotive has made the task of automotive ECU design and system integration much more complex. Increased safety and security requirements in new vehicle architectures are common, with safety requirements in particular adding significant challenges to system hardware and software design. Communicating safety relevant data to the driver via a safe human machine interface (HMI) will only become more complex as the amount of safety content increases. System designers and integrators are faced with the task of deciding how best to solve this challenge from a hardware and software perspective. This paper examines in detail how the hardware and software architectures of today’s automotive safe HMI systems, such as instrument cluster and heads up display, must evolve to support the more complex safety data produced by ADAS and autonomous systems. We will also examine how these challenges were addressed by other industries with similar safe HMI requirements.

The UX of a product increasingly defines the purchase decision — the interface always wins, in other words. Working with many different products over the years, we derived some common patterns of user experience that every embedded HMI should follow, with a special focus on touch HMIs. These patterns have been evaluated by us but are also backed by research from the whole UX community. These patterns span the domains of status/feedback, perception of speed, layout tips as well as wording and icons. The audience will take away concrete ideas on how to evaluate their own HMI and also how to directly improve it. Using these patterns, any HMI team member can make sure that their HMI at least doesn’t harm the product — and maybe even delight their users! With these UX patterns on their hand, any HMI team member can make sure their HMI follows validated guidelines that make the product usable and useful.

Compared to desktop computers and mobile devices like smartphones, embedded systems suffer from low-level performance. Although there are many good reasons for this, users of embedded devices expect a similar performance as on the smartphone in their pocket. The authors will show a clever way to overcome this dilemma. Hands on real hardware they explain and demonstrate how user interaction can be of high-performance on low-level embedded systems. The audience will experience two main aspects of user acceptance: an adapted conceptual design of the user interface and a declarative modelling language that is optimised for the underlying technical platform. Despite the technical limitations of the device users shall get the impression of a smooth and performant HMI. The key is to avoid computationally intensive features by design. Nevertheless, it is possible to make careful use even of features like scrolling, zooming, swipe gestures and animations in known applications.

Today, there is a tremendous number of IoT solutions available and one is spoilt for choice. LPWAN here, 5G there, all promising longer battery life, extended coverage, scalability, device/communication security and, most of all, drastic cost optimization. The fact is that it is not so easy to understand their positioning and find a suitable solution. At first glance, they seem to be opposed in every way (LPWAN uses an unlicensed spectrum while 5G uses an upgraded LTE-4G carrier version). However, they answer the same needs even if their use cases may differ. Therefore, are they really different or in fact complementary to each other? The presentation will go through the various existing and mature solutions (IPs, protocols, security issues and cloud providers) with a focus on their respective business model and ability to drive the growth of the so-called golden age of IoT.

The following presentation provides an overview of LoRa Cloud™, which is the next step in the evolution of LoRaWAN® networks. This presentation will describe the implementation of full lifecycle device and application services, dramatically simplifying the process of developing managed-endpoint solutions and making LoRa® devices and the LoRaWAN protocol more accessible to application developers. By analyzing a complete endpoint-to-Cloud IoT solution example, the user will be taken on a step-by step journey through geolocation and device join services, with a highly secure provision system enabling a fully secured device on-boarding and network join.

Low-power wide-area networks (LPWANs) are a key technology in building up the Internet of Things. A major hurdle during the installation and operation of LPWANs is the power supply covered by small batteries: These batteries have to be recharged or replaced depending on performance like duty-cycle, data rate, coverage and applied sensors. MIOTY, a LPWAN protocol based on the ETSI standard TS103357 with minimum power consumption, is well suited to extend the operation time. Even further extension can be achieved by the energy harvesting using ambient energy like light, heat or motion: Small thermal gradients or vibrations and even indoor light are sufficient to power the MIOTY communication without any battery and transmit data every couple of minutes. We will present measurement results and performance data of a unique combination of energy harvesting and efficient energy management for a fully self-powered, maintenance-free MIOTY node operated by light, thermal gradients or vibrations.

Cyberattacks and data theft are notoriously prevalent risks in the IoT sphere. Devising a robust security strategy is therefore vital and requires sound security considerations at each step of a project relying on an IoT system. We developed a threat and risk analysis methodology for LoRa-based IoT systems and applied it to an industrial solution for collecting, transmitting, managing and processing data. Both the IoT solution and our security analyses were applied to four use cases: geolocalisation, predictive maintenance, ergonomics, and performance analytics, which were deployed and assessed in several industrial settings (aeronautics, chemical, energy) with specific concerns. Furthermore, we designed a general framework meant to facilitate the classification of IoT systems from a security perspective. In this paper we describe our analysis methodology, provide an overview of the obtained results and security classification and present our conclusions and experience.

Nowadays, virtualization is widely used to produce devices that are flexible and portable as well as safe and secure. In this context, we define Virtualization as the ability to run one or more operating system (OS), named guest, on top of another operating system, named host. Debugging Virtualization Systems is not an easy task due to diversity of the different software components running on the same Hardware platform. Visibility into several OS kernel data structures, including those associated with threads and OS kernel modules is crucial in this scenario. In this session, after giving a brief introduction on Virtualization Systems, we will discuss design and debugging (OS kernel and applications) considerations when developing a system with virtualization. In this scenario, we will describe in details the different embedded systems design and debugging strategies, showing benefits, drawbacks and use cases.

Embedded Systems are available in a wide range of performance levels. Debugging of single core systems is very simple with the tools available. It gets more complicated on multicore SoCs due to its real parallel nature. On virtualized systems its even more complicated. Debuggers now have to deal with different OS running in parallel with communication and hardware for virtualization. Virtualization itself can be achieved with hypervisors like XEN. Most hypervisros are not designed for Embedded Systems due to constraints like realtime and safety. There are also partitioning hypervisors like Jailhouse. Hardware is partitioned and can't be shared. Realtime and safety are easier to achieve. Now the difficulty is to debug sucha virtualized multicore system. A debugger needs knowledge about the operating systems, the virtualization, the mapping of the peripherals, cores and memory of each guest. The following text will show, how awareness for Jailhouse was brought into the Lauterbach debugger.

The attack surface in IoT embedded devices has grown exponentially as connectivity requirements are increasingly met with the integration of 3rd party libraries and open source components. The TrustZone traditional dual-world separation simply doesn’t work anymore. A new zero-trust model is required to address the intrinsic security threat posed by the resulting monolithic multi-source firmware. In this session, Dr. Sandro Pinto and hardware security expert Cesare Garlati propose a new ground-breaking approach based on hardware-enforced, software-defined separation for multiple equally secure functional domains. They start by explaining why the dual security-policy model of TrustZone is no longer enough to meet the requirements of modern IoT applications and then they detail how the proposed TEE is able to provide an unlimited number of equally-secure functional domains. Finally, they will show a live demo of a working prototype running on a Cortex-M7 platform.

Modern safety-critical systems such as autonomous vehicles or industrial robots are constantly and rapidly increasing their complexity with cloud-connected and dynamically deployed functions. Keeping such systems “safe” may require reducing their complexity by separating critical and non-critical parts. Safety certification is one requirement for software to be used in highly regulated industries. The Xen Project, a secure and stable hypervisor that is used in many markets, has been exploring the feasibility of building safety certified products on top of Xen for a year. This session discusses motivations and challenges of making safety certification achievable in open source. The audience will get a look into the process the Xen Project followed and highlight lessons learned along the way. The talk will cover tech enablers, processes, tooling changes and community challenges offering an in-depth review of how Xen Project is approaching this exciting and challenging goal.

Running Android has a lot of benefits; from users being familiar with it, to applications and libraries already existing for it. But getting Android up and running on your particular hardware platform is probably not all that simple. SPURV is a research project with the goal of running Android inside of a container for deployment on embedded platforms. Not only that, but also to provide direct access to the GPU and interoperability with Wayland applications. On a high level SPURV is built on top of the Android Open Source Project (AOSP) and systemd-nspawn. The host OS, which has to be Linux & Wayland based, is able to run a normal desktop in parallel with SPURV. This enables the user to run for example Libre Office and Fruit Ninja side by side.

The growth of IoT devices creates new SoC feature requirements. FPGAs have traditionally provided ways to fill processor gaps, but have lacked integration of the microprocessor and security cores to enable it as a standalone edge solution. PUF technology enables devices to have a completely unique identity based on the intrinsic properties of the device providing a root of trust for identification and key generation, enabling secure boot and data encryption. Combined with factory provisioning each device is uniquely authenticated. Private keys never leave or stored in the device. Next generation uSoC FPGAs provide programmable fabric and an embedded MCU for interfacing, memory buffering, always on processing and acceleration while a PUF based root of trust provides unclonable security to validate device firmware and encrypt data. These features provide embedded developers an extremely capable and secure device with unprecedented reductions in cost, power and product form factor.

CHARIOT (Cognitive Heterogeneous Architecture for Industrial IoT) is a research project granted under the IoT-03-2017 - R&I on IoT integration and platforms as a Research and Innovation topic. CHARIOT provides a design method and cognitive computing platform supporting a unified approach towards Privacy, Security and Safety of IoT Systems. This publication describes the CHARIOT system architecture and particularly a Privacy and security protection method building on Public Key Infrastructure technologies, a Blockchain ledger in which categories of IoT physical, operational and functional changes are recorded and affirmed, a Fog-based decentralised infrastructure for Firmware Security integrity check, an accompanying IoT Safety Supervision Engine as a novel solution to security challenges of IoT data, devices and functionality, a Supervised Cognitive System, analytics/prediction models enabling high security/integrity of Industrial IoT supported by static code analysis of IoT devices.

Consolidation of Security and Connectivity at the Device Edge is critical to make IoT successful. Standards and Ecosystem are key for this success and build competitive offerings. Security is not “one fit all”. Risk Analysis governs the choice of security solutions and certification levels adapted to a given market. With new standards (e.g from ETSI, GSMA, GP, ...), there is an opportunity to propose security solutions integrated on devices capable to match different IoT actors’ security requirements, and to guaranty interoperability and fast IoT deployments. This hands-on workshop will detail prototypes and application examples (based on standards) of sensitive IoT use cases to illustrate the ROI from hardware-based IoT edge security. It will cover secure cloud communications and the management of the refurbishment of a gateway from one cloud service to another one, access to sensitive device peripherals for smart lock and smart metering and device attestation based on standard schemes.

Smart grid and smart meters adoption is growing rapidly as companies encounter increasing security regulations, a need to automate readings and remotely confirm service status. It is expected that there would be more than 2.5 Billion IoT smart devices in utilities by 2023. The unprecedented growth makes it a growing target for cybercriminals; exposing individuals, their data and their privacy to risk if left unaddressed. New deployments are requiring utility solution providers to support end-to-end security in the next generation of smart meter’s.In order to ensure threat mitigation at each stage of a smart meter’s life cycle, we need to answer key questions, • How to include root of trust in each smart meter when millions of devices are getting deployed? • How to ensure the data communication between the device and the cloud is private? • How to trust that the firmware update source? This session will discuss the privacy and security implications for utilities deployment at scale.

Historically Automotive control units were literally read only. Functionality has been defined by the developer at the very beginning with no major changes over lifetime. Number of write cycles for Flash memory was a no-worry. Now systems become much more complex with ECUs being consolidated into domain controllers hosting multiple functions on one SOC. Introduction of Android makes cars look like mobile phones but with a higher life time of 10-15 years. Together with OTA updates this results in many more write cycles that might make the flash wear out before end of life of the car. Fragmentation suddenly is observed to have an impact on performance at mobile phones. This might break an automotive system if it happens there. Issues like FCA’s endless loop update from 2018 or the Spotify bug from 2016 with writing 5GB per hour to flash puts further risk on future systems. The paper describes those effects more in detail and suggests measures to mitigate the risks.

In the field of information technology, public databases are established for known cybersecurity attacks and are used for the analysis of systems and the development of security measures. Up to now this was not the case in the automotive industry. In this article we show a feasible concept for the creation of an automotive vulnerability database and an extensive collection of attacks which can serve as a first data set for the database. We also present use cases from the vehicle domain (threat analysis, security testing, access control), which are being investigated in three research projects at the Institute of Energy Efficient Mobility (IEEM).

The security of immobiliser and Remote Keyless Entry systems has been extensively studied over many years. Passive Keyless Entry and Start systems, which are currently deployed in luxury vehicles, have not received much attention besides relay attacks. In this work we fully reverse engineer a PKES system and perform a thorough analysis of its security. Our research reveals several security weaknesses. Specifically, we document the use of an inadequate proprietary cipher using 40-bit keys, the lack of mutual authentication in the challenge-response protocol, no firmware readout protection features enabled and the absence of security partitioning. We implement a full proof of concept attack allowing us to clone a Tesla Model S key fob in a matter of seconds with low cost commercial off the shelf equipment. Our findings most likely apply to other manufacturers of luxury vehicles including McLaren, Karma and Triumph motorcycles as they all use the same system developed by Pektron.

The autonomous car is a game changer in many ways, also in terms of safety. Today, safety goals are achieved by end-to-end concepts, with the driver as fall back. Once the computer is exclusively controlling, the availability of communication paths becomes crucial to allow fail operational systems. Vehicle safety is then requiring a combination of functional safety and reliability. In this context, the view on Ethernet ICs is changing. While current car networks usually do not impose safety requirements on connectivity ICs, IC vendor start to see the demand for products with a certain safety requirements and ASIL level. Beyond marketing figures and ticking off feature lists, there is more needed to compare the value of integrated safety features.This paper we will explain the context of functional safety in networking ICs, examples and outlook how the network will eventually support failure prevention. Finally, the paper will provide background to methods of implementing the ISO26262.

While modern vehicles are increasingly digitized and networked, security attacks may lead to malfunctions of vehicles on a massive scale. For instance, a cyber-attack through over-the-air (OTA) update may install malicious software on electronic control units (ECUs) in numerous vehicles, possibly resulting in severe accidents. To reveal security threats and their potential impact on safety, security analysis is conducted in the early stage of automotive engineering. In ECSEL Joint Undertaking project SECREDAS we investigate a new approach to automotive safety-security co-analysis. This paper reports a co-analysis method which extends Systems Theoretic Process Analysis (STPA) and a case study of analysing an OTA update system. The case study shows that the STPA-based method enables a close integration of safety and security analysis, as the entire socio-technical system is considered as a whole in achieving security and safety.

Just as mobile phones have become ubiquitous handheld computers, so too connected and autonomous vehicles are quickly becoming moving edge computers. Users will require increased connectivity and personalization to meet their evolving needs over the vehicle life cycle - in a secure manner. OEM future app stores will allow over-the-air (OTA) service/application downloads for vehicles, from suspension and powertrain upgrades to infotainment and cockpit design. To enable this revolution, in-vehicle computing platforms (ECUs) are required to support advanced Service Oriented Architecture capabilities and integrate with the OEM cloud. Here we will describe the architecture for the next generation of SOA ECUs, which doesn't only enable the service-oriented vehicle, but creates an in-vehicle micro-cloud infrastructure which echoes the enterprise cloud infrastructure used to support vehicle fleets. Thus, providing uniform design concepts, easier integration and unified management and security.

Modern domain specific designs require optimized area and features to deliver high efficiency and performance. A truly scalable processor architecture permits the design of MCU core that are scalable in pipeline depth, extension support, and other key features. In this talk, SiFive will demonstrate how to create a heterogeneous multi-core microcontroller that combines many powerful processor cores alongside simpler, low power essential cores that can be treated as a holistic entity by software and system design.

We describe Embench™ (for Embedded Benchmark). Unlike Dhrystone and CoreMark benchmarks that are single synthetic programs, Embench 0.5 suite has 20 real programs. Like SPEC, the single performance number that people will promote is the geometric mean of performance relative to a reference platform. Novel features of Embench include reporting code size as well as program performance and to measure interrupt latency and context switching. The Free and Open Source Silicon (FOSSi) Foundation sponsors Embench. We initially aim to evaluate microcontrollers that support ≤64KiB of code and read only data and ≤16KiB of data. We will demonstrate Embench’s value by contrasting its performance evaluation of several embedded systems to Dhrystone and CoreMark. Our hope is that publications of performance for embedded computers will include Embench along with Dhrystone and CoreMark, and that Embench will eventually retire these much older, single, synthetic benchmarks to the dustbin of history.

The paper presents a customizable, highly scalable and RISC-V compatible processor architecture for FPGA-based systems. A key aspect of the ParaNut architecture is a special concept of parallelism, which combines advantages of SIMD vectorization and simultaneous multi-threading in one architecture. At the same time, the complexity of a single computing core is minimized in order to save area and power. Speculation techniques are generally avoided in order to make the processor robust against security flaws such as Spectre and Meltdown. ParaNut/RISC-V processors are planned to be used in several application fields including computer vision, deep learning, and Internet of Things. The present implementation passes the RISC-V compliance tests (RV32IM instructions) and is thus compatible to the standard RISC-V toolchain. Preliminary experiments on a Xilinx 7 platform show 0.87 CoreMarks/MHz using 1 core and 3.47 CoreMarks/MHz using 4 cores, revealing an almost perfect speedup of 3.99.

From a semiconductor hardware perspective, tradeoffs between the three key metrics of Power, Performance and Area (PPA) are well known and critically important in the optimization of a design. In this paper, results from a set of redefined “software PPA” metrics are examined. Based on porting multiple real-world production microcontroller security and machine learning applications from Arm Cortex-M cores to PULPino RISC-V cores, these revisited metrics were studied. Two different security applications, both functioning as independent “blackbox” security enclaves, were analyzed. Using the redefined definitions, performance in terms of execution cycle counts and dynamic instruction path length, power in terms of silicon dissipation plus memory access types and rates, and static code size as a proxy for area are presented and compared.

RISC-V is being used in complex real-time heterogeneous systems. The software executing on such systems needs to be tuned to provide the best performance possible. Developers need insight into the operation of the software and its interaction with the underlying hardware structures, including NoCs and CPUs. A key element of this is cycle accurate processor trace, which provides information on how many cycles code takes to execute, whether there are stalls and dependencies and how long they last. System designers can use these insights to make optimizations and achieve efficiency gains. We present a cycle accurate instruction trace encoder algorithm which has been implemented using as the primary input the interface proposed in the RISC-V Processor Trace working group. The presentation will illustrate how the encoder’s capabilities - including filtering, matching and SoC-wide cross-triggering - can be used to produce significant improvements in overall system performance.

Choices we make as software engineers developing embedded systems can have vast impacts on the quality of code. These choices are not only about operating systems, programming languages or software architectural solutions, but it is also about how code is constructed and used. Minimizing code complexity, structuring code into components, managing code reusage and other steps that are crucial to code quality are seldom addressed in requirements and are often forgotten. This talk will go through some rules of thumb, such as coding practices, programming techniques, and other guidelines for software development. It will be a practical approach on how to make software easier to maintain with higher quality by following these rules, and in the end create safer and more secure systems.

Are you afraid of finding critical coding bugs too late? Would you like to have evidence that your code either self-written or not is free from overflow, divide-by-zero, out-of-bounds array access, and other run-time errors before you use it in safety and security critical systems? Do you need to comply with safety and security standards or guidelines like MISRA, SEI CERT-C, ISO/IEC TS 17961? In this presentation, I demonstrate sophisticated static analysis methods that verify and prove the absence of run-time errors and vulnerabilities in the source code at the unit and integration level. Utilizing formal methods (with sound implementation) that consider all potential inputs, controls, and data flows without code execution, organizations will gain confidence that the software they rely on is safe and secure. This gives organizations more than an early error detection tool, it reduces testing and verification costs, and makes code quality transparent across the entire team.

Introducing static code analysis tools into the development process can be difficult, with an overwhelming number of standards, rules, and practices to navigate. This can make the adoption of static analysis challenging, as unoptimized configurations can lead to false alarms, significant pains, and at worst, teams abandoning the idea of introducing static code analysis tools into their process altogether. To reduce the team’s reliance on the perfect static analysis configuration, and the decision-making burden of the user reviewing warnings, teams can now use AI to automatically identify static analysis warnings that represent the most risk and are most critical to fix. In this presentation, we will share how to use artificial intelligence and machine learning to augment the process of prioritizing warnings, making it much easier to introduce static analysis into the software development lifecycle, and continue to use the technology efficiently.

Run/stop debug combined with instruction trace was the technology for analysing embedded software. Today finding bugs at the instruction level is unmanageable as devices lack trace pins, operate at high-speed or have multi-core processors. Instead, event annotations can be used to analyse the dynamic operation and the timing of complex software stacks on Cortex-M systems during execution. It is available for all Cortex-M devices, does not require trace and offers detailed insight into "black-box" software components. Multiple views to run-time behaviour, including task scheduling and timing provide high-level information about the operation of communication stacks or inter-process communication. Statistic view show infrequent program anomalies or worst case timing. Events are easy to add to user code and many RTOS systems or IoT communication stacks are already annotated. Other benefits include post-mortem system analysis or remote diagnosis of IoT devices.

Static analysis tools are now widely used in industry, academia, and open-source for finding serious defects and security vulnerabilities. Experience has shown that deeper integrations with other tools in DevOps or SecOps environments can drastically increase the effectiveness of static analysis. Most integrations are ad-hoc pairwise connections, which inhibits flexibility and adoption, so there is a need for standards to remove those barriers. This talk describes SARIF (Static Analysis Results Interchange Format) – a new open standard for representing the results of analysis tools. SARIF is being adopted by major tool vendors, and open source tools are being modernized to support it too. This talk will show how SARIF can be used to allow users to get more value from their tools, as illustrated by an example that populates a code review comment stream with static analysis results.

We all know how important vision is in our day to day life, What if we have an edge computing with embedded vision that sees beyond our own physical monitoring techniques? The world is growing fast, edge computing and computer vision are making it easier and smarter. During my session I will be explaining how to develop a computer vision solution with Intel OpenVINO together with edge embedded processing power from Intel which is called Intel UP2 squared AI vision. I will also showcase some business application and scenarios, for example a safety check at the entrance of factory that requires safety kits, if the safety check is not complete the door will not open.

CMOS image sensors made an enormous leap in development in the past years, benefitting from consumer electronic products like cell phones, tablets, etc. This technology boost generated an extensive variety of sensors with MIPI interface, also in the high-quality range. These image sensors convince with both high-tech features and low pricing. The MIPI technology affects more and more fields beyond the primary fields of operation and today, MIPI cameras are a real alternative for applications in industry and automation, logistics, automotive, smart cities and others. This trend is accompanied by a fast growing variety of processors qualified for embedded vision applications, also deriving originally from consumer markets. In short: Today, high-tech components from consumer markets are suitable for embedded vision applications – at competitive prices. Our lecture will give an overview over state of the art and possible application fields in Embedded Vision of MIPI camera modules.

Today’s heterogeneous computer systems combine CPUs, GPUs, and FPGAs with different archi- tectures. GPUs with immense parallelization are best fitted for real-time video and signal processing. On the other hand, FPGAs are ideal for capturing and pre-processing multiple video streams. Therefore, partitioning computational tasks between these computational units and designing the data-paths between them are very important. Close and efficient interaction of the individual components is, therefore, indispensable. With PCIe, modern computers provide a high-speed internal data network between CPU, GPU, and FPGA. However, since communication usually takes place via the CPU, this communication becomes the bottleneck in applications. This paper compares two different implementations for an efficient FPGA-GPU co-design without CPU bottleneck. The discussed implementation reaches a transfer jitter of only 4 μs and utilizes 72% of available PCIe bandwidth without any CPU interaction.

Considering the ongoing surge of interest in embedded computer vision technology, a growing demand for quickly and easily implemented systems exists. ASTERICS is a framework for designing complex image processing systems on FPGAs, including build tools that allow for rapid prototyping. Among others, the ASTERICS framework has already been used to implement complete object recognition systems based on the Generalized Hough Transform or SURF feature detection, but also simpler systems for educational use. This paper presents ASTERICS with a focus on its new system generation tool. This tool allows image and video processing systems to be defined easily by a short textual description in Python syntax. Benefits considering the development effort and time of this approach are described alongside a design example demonstrating the development process.

Machine learning, artificial intelligence, and embedded vision are now commonly used for biometrics, surveillance, automotive, healthcare and other sensitive applications. As they emerge, hackers wonder: How can I take control? Cybersecurity chips on a board can’t protect against every attack, and relying on system-level security can lock you out of markets with stringent requirements. This presentation will provide case studies of attacks that could have been prevented with SoC-level security, and it will describe the direction that attacks are taking. It will describe the assets that different types of EV and AI systems handle and how to set appropriate security levels. Finally, it will provide options for SoC designers to consider to mitigate threats, protect user information, and defend company liability.

Next Generation Graphics – GPU Shader and Compute Libraries Embedded Graphics libraries have evolved from OpenGL to next gen Vulkan libraries. OpenCL and CUDA have been used for many years for GPU compute on a range of SoC devices with powerful embedded GPU chipsets. OpenCL and CUDA were never able to be certified, due to the contributions from many developers. Next generation autonomous vehicles, unmanned aircraft, transportation and even military vehicles will require both graphics, as well as GPU compute to implement DSP or FPGA logic is software, as well as AI. Vulkan libraries are available now and are defined by the Kronos Group, as well as this, a next generation of Vulkan safety critical library for safe Shader and GPU Compute is now available. This white paper will look at Vulkan architectures, embedded system use and the implications for using GPU Compute, where certification may be a critical requirement for ISO 26262, EN50182, IEC 61508, DO178C certifiable embedded systems.

The web and its immense success over the last 20 years had a major influence on technology. It has shaped how we serialize data, consume and provide services and how we develop HMIs. An up to date application framework needs to reflect this. Qt is a popular cross plattform C++ framework with a long history. This presentation will provide a survey how the challenge of the Web is addressed by Qt. The presentation is split into three parts. 1) Consuming and interfacing with web-centric services and APIs from a Qt application. 2) Implementing services and APIs to be consumed by other - web-centric systems - with Qt. 3) HMI development. There are a number of scenarios where an HMI needs to run a web browser. This can either mean an HMI that is implemented using Web-technologies or a Qt HMI needs to be run in a browser. For each of these areas we will look into typical scenarios and how to address them with Qt. We will highlight where Qt really shines and where additional work is left to be done.

With the proliferation of digital displays for cars, appliances, medical devices and more, increasingly complex production GUI software and code is on the way. Both will arrive with rapidly expanding features and depth. There are countless ways for errors to be introduced in such projects. Agile development can help development teams confirm delivery of high quality software for these applications, but the fast iterations that result from agile development can derail test teams who can consume up to have of the development effort with GUI testing. How can product development teams ensure that the GUIs running on their production hardware is a perfect match to their developer’s intent design? Altia will review popular methods for embedded GUI testing -- manual systems, camera-based test systems and more technically advanced approaches. Altia will also present a method that compares baseline GUI designs with the same user interface running on real-world embedded hardware.

Avionics and automotive hardware is ever-evolving, but often the display software doesn’t need to change. CoreAVI has a long history of collaboration with the FACE Consortium to lead the way in the creation of portable display software. Use of open standards including OpenGL®, FACE™, and Vulkan® allows a clear separation of display software and the hardware. This separation benefits developers as it allows them to start work without knowing about he GPU. CoreAVI has introduced a way to use the GPU to composite the visual output of different pieces of display software without requiring them to be rewritten each time a new symbol is added to the display. This compositing maintains the transparency of each pixel and sends them to the compositing application for blending, enabling screen overlays to be run as separate applications and screen geometry. This presentation will detail how existing DO-178C or ISO 26262 application software code can effectively be rehosted on advancing hardware.

Early uses of gesture detection as an HMI began with gaming and entertainment applications on platforms like Microsoft’s Xbox or Nintendo’s Wii, but they required significant computational performance and power. Designers have been less successful using gesture detection technology in broad market applications. Analysts at MarketWatch forecast consumer electronics using gesture recognition technology will grow at a 30.37 percent rate over the next five years. A reason for this is the broad availability of devices and tools using Artificial Intelligence (AI)/Machine learning (ML), which makes the rapid adoption of hand gesture detection as a way to control the human machine interface (HMI) less elusive. This presentation will explore the different approaches and methodologies, including a look at the pros and cons of various hardware platforms (MCU, SoC, ASSP or FPGA) to use when they develop power gesture applications for use products targeting the broad market.

This one day training class uses hands-on exercises combined with instruction to illustrate some basic concepts of Embedded GNU/Linux. Hands on sessions are performed with a toolchain/rootfs built by the freely available Yocto Project, on an embedded board. This enables you to take the course material home and work with it. Limited seats!

Over the course of the last years the need to reduce energy consumption is growing. This workshop focuses on the possibilities for reduction of energy consumption in embedded systems. We argue that energy consumption is a system issue and therefore a matter of making compromises. Energy consumption can be reduced by software, but only so far as hardware allows. There are many things that can be done to reduce energy consumption. The goal is to define an approach for achieving less energy consumption. Also criteria for the selection of an appropriate MCU are presented. Conclusion: Many (unexpected) things can have a big impact on your achievable battery lifetime. Look beyond just the CPU/processor and software in order to achieve better results. Limited Seats! Hands-on Workshop – Laptops will be provided

This class– based loosely on the author’s book Real-Time Agility – is a full-day lecture and practice course to discuss how to use agile methods for the development of real-time and embedded systems. especially planning, organizing, and enacting agile methods in an environment that requires rigor and safety to be addressed. Time is spent on both agile methods and development issues special for embedded systems. As compared with the book, less time is spent on the use of model-driven development and proportionally more time is spent on agile practices.

The impressive growth of the RISC-V ecosystem is on everyone’s lips. Originally developed at UC Berkeley, the free and open ISA promises to bring the innovation and collaboration of the open source community to the hardware world - and to dramatically disrupt the whole semiconductor industry in the process. However, hardware and software engineers used to traditional closed-source proprietary architectures and tools may find difficult to orient themselves in this highly-fragmented galaxy of RISC-V technologies, open source tools and development frameworks. This class will show exactly how to download, build, configure, debug and test a completely free and open source RISC-V system. This class is a must-attend for SoC designers, system architects, and software developers who want to properly implement secure RISC-V systems but don’t want to take the time and the risk of figuring out the necessary moving parts themselves. Laptop: Recommended but not required.

Developing secure embedded devices is becoming more and more difficult. Complex functional requirements are increasingly met with the addition of untrusted 3rd party software. The resulting monolithic firmware presents vastly larger code base, greater attack surface, and increased system vulnerability. When TrustZone is not available, or when its “two worlds” are not suitable for the specific application requirements, developers need an alternative way to shield critical functionality from less trustworthy components. In this class, we’ll show a quick and safe way to add security and separation to ARM Cortex-M devices that don’t have TrustZone. Step by step, we’ll build a hardware-enforced software-defined trusted execution environment capable of enforcing security and separation for a multitude of equally secure “worlds”. We will then configure the trusted execution environment for a real-world 3-zone application controlling a robotic arm, test security and separation, and evaluate overall system performance. Laptop: Recommended but not required. NOTE: a number of development boards will be provided for free to the attendees - Microchip SAME70 XPLAINED.

Android can be used as the basis for any touch-screen system, whether it be mobile or not. As a very customized embedded Linux distribution, Android has a very elaborate and rich set of user-space abstractions, APIs, services and virtual machines. This one-day tutorial is aimed at embedded developers wanting to build touch-based embedded systems using Android. It will cover Android from the ground up, enabling developers to get a firm hold on the components that make up Android and how to customize them. First, we will cover Android's architecture and the Android Open Source Project, the project under which Android's source code is released. We will then dig into the native Android user space and Android's power tools, and cover how hardware support is implemented in Android. We will also go over its custom uses of Linux and see how the kernel is modified to support the Android user space. In addition, we will look at the System Server, the Android Framework and core applications.

The UML and SysML provide very good tools for specifying behavior application systems. Behavior may be specified for individual classes, subsystems, components and use cases with state and activity diagrams. Behavior may also be specified for elements acting in collaboration using interactions diagrams using sequence, collaboration, and timing diagrams. Statecharts, an enhanced form of state machines, form the basis for state behavior in the UML. Activity diagrams, while intimately related to statecharts, are used effectively to model algorithmic behavior and have been significantly extended in the SysML to include behavior that is both continuous in time and value. Sequence diagrams are used to show how collections of individual elements work together in collaboration to produce system-wide behavior. This class – with heavy emphasis on exercise-based learning - discusses these methods and provides practical examples of their use.

1) Tips and Tricks for Efficient C/C++ 2) C/C++ Co-Existence 3) Challenges in multithreading / multicore applications 4) Advanced Debugging Techniques (Live Demo)

With the introduction of C++11/14/17 new best practices have evolved that are reflected in safety programming guidelines. Many practices that have been established for years using C or old-style C++ are now considered obsolete or risky, where better designs and usage of language constructs have been established. For example, plain pointers that dominate old code will be applied only very sparsely and encapsulated in modern safe C++. The use of standard library algorithms allows reducing the risk of loops by better articulating behavior. Encapsulation of primitive types for representing domain values can be done without overhead. This class will introduce new ways to solve problems and demonstrates how to migrate from older practices. In some cases it shows where automated tools can help to avoid them or repair existing code interactively.

If you ever wanted to get started with FPGAs without becoming a hardware expert, or already are a hardware expert who wants to integrate Arm Cortex-M soft CPU IP into their FPGA designs, this workshop is for you. During this workshop, you will get hands-on experience with creating, programming, debugging, and developing applications for Arm Cortex-M in Xilinx FPGAs, through DesignStart FPGA. This workshop will walk you through the creation and updating of the FPGA project (without writing a line of HDL so there is no need to be a FPGA developer). Following creation of the hardware, we will hen explore how to develop the board support package and API's needed along with how to create our final application. The workshop will be hands on so will wrap up with the creation of a in depth example which is interactive and demonstrates all the concepts taught throughout the session. Please bring your own laptop, you will receive further details after your registration. Limited Seats!

If you are working with embedded Linux you will be aware that the Yocto Project is a key component for generating device firmware. This intensive two day workshop will teach you how to make effective use of OpenEmbedded and Yocto Project to create highly functional, reliable system images for your target device. It will show you how to select packages, how to customise system behaviour, and how to create your own meta layers. With the relevant information under your belt you will have your embedded Linux system up and running in no time!

High-Level Synthesis (HLS) tools enable the implementation of algorithms coded in C/C++ as FPGA IP cores. Different RTL architectures can be generated by HLS tools in a short time and the tradeoff between performance and ressource usage can be explored. Furthermore the generated VHDL/Verilog code can be easily verified using the C/C++ testbench. Thus design productivity is substantially enhanced when compared to traditional VHDL/Verilog based design. This hands-on workshop will give an introduction in the design of IP cores for Xilinx FPGAs using the Vivado HLS tool. After an overview of the design flow with Vivado HLS it will be shown how the synthesis result can be interpreted in order to derive measures for optimizations. The influence of data types will be shown and how different interfaces can be easily implemented by using directives. Finally it will be shown how the RTL hardware architecture can be optimized using pipelining, loop unrolling and the optimization of arrays.

Deep learning and artificial intelligence will revolutionize industrial automation applications. Applications such as Preventive maintenance, Defect inspection, Process tracking, Quality optimization, Location and path planning are only a few of the examples that need new more powerful and low cost embedded AI devices. However, with these emerging AI applications comes risks in data protection that must be mitigated. A catalyst is needed to facilitate the development of open source processes and community support to break down barriers. Training and deploying a model in an industrial application takes knowledge best sought from community interaction. Bringing data and model collaboration to embedded developers provides greater mitigation of risks. In this class we will have hands on training that explores techniques that not only demystify these challenges but find solutions through collaboration and sharing of practical knowledge. Computers will be provided.

In these modern times, connected devices must communicate over potential insecure channels. Hackers and reverse engineers can easily discover and extract AES key material by using low budget hard- and software tools. Embedded hardware designers must cope with the fact that even mostly unskilled groups of attackers can reveal keys at costs compared to a dinner meal. Upmost, if one is using a symmetric cryptosystem and the secret keys are shared among all devices, it is obvious that the stronghold of data privacy collapses in every single device if only one fails. This workshop is intended to teach the fundamentals of the AES cryptosystem and how the side-channel-attack differential power analysis (DPA) works. During the second part of the workshop, the presenter will conduct a live demonstration of how the AES key can be extracted out of a standard µC running AES in a µC’s hardware engine. Finally, countermeasures using secure co-processors against common attacks will be presented.

Use cases are easily the most misused feature of the UML. Virtually everyone has questions as to how to best represent use cases, link them to requirements, identify appropriate scenarios, and how to effectively use behavioral models to clearly and unambiguously specify systems.What is even less well understood is the relations between epics, use cases, user stories, and scenarios and how these all play together in an agile development project. Well-known author, Bruce Douglass, lends his decades of experience and shows how to deploy these techniques effectively for real-time and embedded systems development. Special attention is paid on how to make the approach scalable to large systems while not over burdening the specification of small systems