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19. - 20. November 2019
Hyperion Hotel München

Anwenderforum Leistungshalbleiter


Tag 1 - Dienstag, 19. November 2019

Parallele Sessions

09:00 - 19:00
Sessions Tag 1
09:00 - 09:30
Keynote: The Power of Integration Balu Balakrishnan, Power Integrations
09:30 - 10:15
Intensivseminar: Aktuelle und zukünftige Ladegeräte-Topologien für Industrie und Elektromobilität Tobias Fuhr, Finepower  
Most of power electronic devices use well known semiconductor topologies. The scale of their usability is wide and components on the market are optimized for each application (e.g. simple energy transformation, energy storage charging or motor drive). Recently, the need of middle and high-power chargers (in the range of 1kW or 10kW) for automotive industry is increasing. On-board-chargers and wireless charging stations for parking lots and garages are the most frequent applications. This article is focused that application. It also describes features a few inverter examples. Company Finepower is on international market of power electric inverter development more than 15 years. Using the experience of Finepower development department provides inverter topologies overview covering one and half decade. Content: 1. AC/DC converter – Power Factor Correction (Standard, Bridgeless, ...) 2. DC/DC converters: Unidirectional (LLC, Phase-Shifter), Bidirectional (DAB) 3. Wireless Charging: Schematic overview, Transfer characteristics 4. Outlook For all chapters, the requirements on the Semiconductors can be pointed out. (longer abstract / article available as PDF)
10:15 - 11:00
Kaffeepause in der Ausstellung
11:00 - 11:30
Analysis of PCB parasitic effects in a Vienna Rectifier for an EV battery charger by means of Electromagnetic Simulations Simon Muff, Keysight  
This work investigates the impact of the PCB parasitics on the performances of a SiC three-level t-type rectifier used for electric vehicle battery chargers. The high switching frequency and the fast raising edge of the rectifier enables a very efficient design. On the other hand, as the time derivative of the current increases (as a rule of thumb we can set 1A/ns as a breaking point), PCB parasitics start to play a significant role and, if not properly taken into account, may cause the degradation of the performances or even a design failure. Industry standard EDA (Electronic Design Automation) tools can be used to extract a model for the PCB so that all the effects introduced by the physical realization of the board layout can be included in the analysis. For the current work the software Advanced Design System by Keysight Technologies was used to extract an S-parameter based model of the PCB and co-simulate it with the circuit components. Results obtained with and without the PCB model are compared for two different design iterations.
11:30 - 12:00
All Roads Lead to Rome: SiC, GaN and Si Technologies in Switch Mode Power Supplies Francesco Di Domenico, Infineon Technologies  
The design of SMPS for server, telecom and general industrial applications is in continuous evolution, with more and more challenging requirements in matter of efficiency, power density and environmental/cooling conditions. Power semiconductors are traditionally key components in any SMPS design, from both performance and cost point of view. A crucial step in any design is the decision of the proper combination between power conversion topology and power semiconductor technology in order to address the required performance, taking of course the cost into account. Today new semiconductor technologies, like wide bandgap, are available in the market besides the traditional silicon based ones. This gives more options to the decision makers, but does not mean that the decision is easier, since more aspects have to be considered especially with regard to the selected topologies. The paper begins with a brief summary of the key parameters of Si Superjunction (CoolMOSTM), GaN (CoolGaNTM) and SiC MOSFET (CoolSiCTM) technologies for 600-650V-rated devices. Then the core part of the paper is a performance comparison of different combinations of technologies and topologies selected for the PFC and isolated HV DC/DC stage of a high efficiency SMPS for server and telecom/hyperscale datacenter applications. On this purpose, two relevant case studies will be analyzed: › 12 Vout / 1 kW 80 PLUS Titanium › 48 Vout/3 kW, ηpeak= ~96.5 - 98% Finally, the positioning of the three technologies is presented based on the achieved results. Also the technical value drivers of each technologies in HP SMPS applications are highlighted.
12:00 - 12:30
Technologies and Benefits of the DIPIPM Family Dr. Hussein Khalid, Mitsubishi Electric Europe; Philipp Jabs, Mitsubishi Electric Europe  
Designers of inverters for small AC motors in consumers’ and general purpose industrial applications are required to meet increasingly challenging stringent efficiency, reliability, size, and cost constraints. Classically, many of such small inverters designs utilize discrete power device packages along with the necessary auxiliary components needed to realize the interface, drive, and protection functionalities. Clearly, however, there are several problems associated with this approach. One drawback is the high manufacturing cost associated with mounting and isolating multiple high voltage discrete components (600V~1200V blocking voltages range). In addition, relatively large and complex PCB designs are required to meet all of the spacing and layout requirements of the drivers and discrete power devices combination. Another equally perplexing problem is maintaining consistent performance and reliability when the characteristics of the drivers and power devices are not properly matched. An alternative solution to these problems is to use an integrated power module that contains all the required power devices along with matched gate drivers and protective functions integrated in low-voltage and high-voltage ICs (LVIC & HVIC). The DIPIPM™ concept was originally developed for the needs of high volume inverterized consumer applications like washing machines, air-conditioners, refrigerators etc. Over the past 22 years, the DIPIPM™ concept received very positive market acceptance with more than 470Mio pieces been manufactured by Mitsubishi Electric in different packages, voltage and current ratings. In the lower power range (few hundreds Watts ~ few kilo Watts), the new very compact surface-mount package IPM (MISOP™) as well as the SLIMDIP™ utilize the latest reverse conducting IGBT (RC-IGBT) technologies. For the intermediate power range (few kilo Watts), the Super Mini DIPIPM provides high performance advantages for a wide range of applications realized with the utilization of the latest generation of both Si and SiC devices. At the higher power-range, for industrial drive applications (few tens kilo Watts), the new DIPIPM+™ series was developed as an “All-in-One” solution addressing the specific needs of compact industrial 400VAC-inverters in a CIB (Converter Inverter Brake) configuration. The success of the DIPIPM™ family is the direct result of advantages gained through optimized integration technologies. Some of these advantages include the following: (1) Reduced design time and improved reliability offered by the factory tested, built-in gate drive and protection functions, (2) Lower losses resulting from simultaneous optimization of power chips and protection functions, (3) Smaller size resulting from the use of bare power die and bare control chips, and (4) Improved inverter manufacturability resulting from lower external component count and isolated heat sink mounting surface.
12:30 - 13:45
Mittagspause in der Ausstellung
13:45 - 14:15
Keynote: SiC: From Niche to Mass Production Christian André, ROHM Semiconductor  
14:15 - 14:45
Strukturelle Integrität von Leiterplatten und Verbindungstechniken für die Leistungselektronik Holger Krumme, HTV  
Strukturelle Integrität von Leiterplatten und Verbindungstechniken für die Leistungselektronik Dipl.-Ing. (TU) Holger Krumme, Managing Director – Technical Operations HTV Halbleiter-Test & Vertriebs-GmbH Für die zuverlässige Funktion einer Baugruppe, insbesondere für Leistungsbauelemente, ist die strukturelle Integrität der Leiterplatte und auch der angewandten Verbindungstechniken, meist Löten und/oder Einpressen, von hoher Bedeutung. Um diese zu bewerten gibt es unterschiedliche, zerstörungsfreie und zerstörende Analysemethoden, welche hier beispielhaft dargestellt werden sollen. Zu den zerstörungsfreien Analysemethoden zählt beispielsweise die Durchleuchtung des Prüflings mittels Röntgenstrahlung. Hierbei können Auffälligkeiten, wie beispielsweise fehlerhafte Innenlagenleiter oder Durchkontaktierungen, detektiert werden. Außerdem ist es möglich, den Hohlraumanteil verdeckter Lötstellen, nicht nur von Ball Grid Arrays (BGA) und Land Grid Arrays (LGA), sondern auch Bottom Terminated Components (BTC) wie z. B. MLFs/QFNs (Micro Lead Frame/Quad Flat No Leads Packages), die häufig neben den Signal-Kontakten auch eine zu verlötende Wärmesenke haben, deren Lötstellenqualität insbesondere für Leistungsbauelemente von hoher Wichtigkeit ist, zu kontrollieren. Zudem können bei dieser Methode auch Lötfehler, wie Brückenbildung oder der Head in Pillow-Effekt, festgestellt werden. Viele Kriterien einer Leiterplatte beziehungsweise Baugruppe lassen sich jedoch nicht zerstörungsfrei prüfen. Um einen umfassenden Einblick in den Prüfling zu erhalten, werden deshalb häufig Schliffbilder angefertigt, mithilfe derer zahlreiche Aspekte, die beispielsweise auch in der IPC-A-600- Richtlinie behandelt werden, überprüft werden können. Neben der Laminat- und Leiterintegrität lassen sich in Schliffbildern beispielsweise auch die Ausbildung der intermetallischen Phasen in Lötstellen oder die Kontaktgebung bei Einpressverbindungen untersuchen.
14:45 - 15:15
Enrich the Connection to SiC Simon Kleefeldt, Mektec Europe  
Low inductivity switching of SiC requested some new connection methods which helps to gain the potential of this new chip generation. One possible solution is to use a double layer FPC technology, which fits pretty good into the power modules: The MOT is between 150 to 170°C or above and the break through voltage of 25µm Polyimide is around 7,8kV. The FPC can have two parallel layers which carry the switching lines from the control board to chip. The interconnection pad can also be a single sided pad with double sided access to enable a welding process like laser welding or ultrasonic welding. Alternative standard connecting processes like wire boning (Al, Au, Cu) or soldering are possible as well as new connecting processes like sintering. A new chip generation might need some changes in the surroundings. The FPC can be an enabler for this opportunities.
15:15 - 16:00
Kaffeepause in der Ausstellung
16:00 - 16:30
Boosting Performance of a New Generation of Power Converters with GaN ICs Eric Moreau, Exagan  
GaN-on-Silicon power devices are recognized as a key technology to sustain future power converter systems roadmaps in the field of IT electronics, renewable solar and emission free automotive applications. Exagan manufactures proprietary G-Stack™ 200-mm’s GaN-on-Silicon technologies into high volume production to accelerate GaN adoption. G-FET™ & G-Drive™ Exagan product portfolio provides the GaN-on-Silicon solutions that set new ultimate tradeoffs for new generation of power converters, enabling higher power density, better power efficiency and perfect fit for system cost objectives. This paper will present latest use case demonstrators from few ten to kilo watts range applications leveraging on easy to implement and robust G-FET™ & G-Drive™ products and using cost effective G-Stack™ 200-mm’s GaN-on-Silicon.
16:30 - 17:00
Chip-Temperatur - Licht ins Dunkel bringen Dr. Martin Schulz, Infineon Technologies  
Die dominante Größe zur sicheren Bestimmung der Lebensdauer eines Designs ist die Chiptemperatur bzw. der Chiptemperaturhub. Allerdings herrscht auf dem Chip eine Temperaturverteilung und "die Chiptemperatur" gibt es so nicht. Was also messen? Und wie? Und wie diese Messung interpretieren? Der Vortrag zeigt Vorgehensweisen, Messtechnik und die daraus hervorgehenden Vor- und Nachteile. Darüber hinaus ist die Interpretation von Messergebnissen Teil des Inhaltes, ebenso die Definitionen und Unterschiede zwischen Chip-Temperatur Tj, und der virtuellen Sperrschicht-Temperatur Tvj. Insbesondere lernt der Zuhörer, wie die eigene Messung zur Ergänzung von Simulationen genutzt wird und die Bestimmung der Lebensdauer sichert. Der Vortrag baut auf eigenen Messungen aus dem Labor auf, die für die Klärung der Zusammenhänge notwendig waren.
17:00 - 17:30
Barrier Insulation Evaluation and Research (BIER) Markus Stöger, RECOM Engineering  
Der Beitrag geht kurz auf die Effekte von hohen Schaltgeschwindigkeiten und daraus resultierende Probleme beim Ansteuern von Transistoren und auf den auftretenden Stress von Isolationsbarrieren, insbesondere bei Highside Gate Ansteuerungen ,ein. Der Effekt der Teilentladung soll veranschaulicht werden, und auch die nicht ganz trivialen Einflüsse auf die Teilentladungseinsetzspannung sollen näher beleuchtet warden. Auswirken von Teilentladung auf organische sowie anorganische Isolationsmaterial sollen erleutert werden. Des weiteren wird der Qualifizierungsprozess für Gate Drive Power supplies im Hause Recom erklärt. Der Vortrag richtet sich in erster Linie an Leistungselektronik-Designer,aber auch Laien bekommen einen Eindruck auf mögliche Probleme durch schnelles schalten/miniaturisierung bei Isolationssystemen
17:30 - 18:00
Höherer Wirkungsgrad und Leistungsdichte mit Advanced Synchronous Reverse Blocking (A-SRB) Dr. Mario Ackers, Toshiba Electronics Europe  
Advanced Synchronous Reverse Blocking (A- SRB) is a new Toshiba circuit technology that dramatically reduces switching losses in bridge circuits such as inverters, DC/DC converters or PFC. In order to improve efficiency, there is a trend of making use of transistors based on wide bandgap materials such as GaN or SiC. However the costs of such technologies remain considerably higher than for Si based components. For a cost-effective system, innovations in circuit design are therefore required to achieve the maximum possible efficiency when using today’s silicon-based components. The validity of this approach is also confirmed by the expected limitations of supply for Wide Bandgap devices in the coming years. It is expected that several applications required alternatives solutions that provides significant improvements to increase efficiency and power density by utilizing existing Superjunction technology. The paper covers the following topics: 1. Introduction of A-SRB 2. Explanation of the A-SRB topology and function 3. Achievable improvements by utilizing A-SRB 4. Application examples 5. Future outlook
18:00 - 19:00
Get-together und Networking in der Ausstellung

Tag 2 - Mittwoch, 20. November 2019

Parallele Sessions

09:00 - 17:00
Sessions Tag 2
09:00 - 09:30
Keynote: SiC Performance at the Price of Silicon Bruce T. Renouard, Pre-Switch
09:30 - 10:30
Intensivseminar: Bestimmung und Auswirkung parasitärer Effekte von Wechselrichter-Aufbauten Dr. Christian Römelsberger, CADFEM  
Mit zunehmender Leistungsdichte und neuen Halbleitertechnologien steigen die Herausforderungen in der Entwicklung von Wechselrichtern und DCDC Wandlern. Mit kürzeren Schaltflanken werden die Auswirkungen parasitärer Induktivitäten im Schaltungsaufbau immer drastischer. Z.B. entstehen Schaltspitzen, die die Halbleiter zerstören können, es werden parasitäre Oszillationen angeregt, die unter anderem zu Emissionen führen. In diesem Vortrag wird aufgezeigt, wie mit Hilfe von Feldsimulation die parasitären Induktivitäten und daraus die Auswirkungen auf das Schaltverhalten bestimmt werden können. Die Einbindung von Simulation in einer frühen Entwicklungsphase führt hierbei zu einem großen Erkenntnisgewinn und hilft dabei Redesigns zu vermeiden. Beispielhaft werden diese Methoden an einem Halbbrückenmodul und an einem DC-Link aufgezeigt. Hierbei wird ein spezielles Augenmerk auf einfache Simulationsgrößen wie die Loop-Induktivität des Kommutierungskreises gelegt und auch darauf eingegangen, wie ungleiche Stromverteilungen bei parallel geschalteten Bauteilen entstehen und welche Auswirkungen dies hat.
10:30 - 11:15
Kaffeepause in der Ausstellung
11:15 - 11:45
Einführung in den Schutz von SIC-MOSFETs Olaf Bendix, Infineon Technologies  
Infineon Technologies AG provides a variety of SiC MOSFETs in power modules as well in discrete package. The advantage of high power density and low gate charge leads to increasing number of applications. However, these SiC MOSFETs haves to be controlled. The gate driver interfaces the micro-controller and the high power switches which is shown in Figure 1. The gate driver provides also protection functions for the SiC. At the one hand-side, the driver amplifies the small signal from the μController (several μA) to a gate signal (several A). At the other hand side, the driver IC delivers handshake signals and short circuit protection via DESAT signal in this case. A major challenge is the short circuit protection of the application. For SiC MOSFETs the maximum time for a safe short circuit shut down is about 2 μs. This paper provides an application design flow for tuning the protection functions to fulfill the SiC MOSFET short circuit requirements. It will also discuss the advantages of two different protection techniques for short circuit.
11:45 - 12:15
Totem-Pole-PFC mit SiC-MOSFETs zur Anwendung in Automotive On-Board-Chargern Dr. Christian Felgemacher, ROHM Semiconductor  
In diesem Beitrag wird die Anwendung von SiC Trench MOSFETs in einer einphasigen AC/DC Wandlerstufe dargestellt. Zum Einsatz kommt eine Totem Pole PFC Topologie, die durch den Einsatz von WBG Leistungshalbleitern eine leistungsfähige Alternative zu anderen einphasigen PFC Topologien bietet. Neben einer Darstellung einiger an einem kompakten Testaufbau gewonnenen experimenteller Ergebnisse wird auch die Einsatzmöglichkeit dieser Wandlerschaltung in Anwendungen wie On-Board Ladegeräten von Elektrofahrzeugen aufgezeigt.
12:15 - 13:30
Mittagspause in der Ausstellung
13:30 - 14:00
Keynote: Challenges in power electronics packaging and ways to tackle them Peter Sontheimer, SEMIKRON  
In dem Vortrag wird es darum gehen, dass die Trends der Leistungselektronik über die Zeit immer gleich geblieben sind und gleich bleiben werden: höhere Packungsdichte und höhere Zuverlässigkeit sowie niedrigere Systemkosten. Ausgehend davon beleuchtet der Redner die Herausforderungen, die sich daraus ergeben, und zeigt entsprechende Lösungen auf.
14:00 - 14:30
Enabling the EV revolution through Silicon Carbide Power Semiconductors Avinash Kashyap, Microchip  
A recent trend in the semiconductor market is the widespread adoption of silicon carbide (SiC) devices, including both Schottky barrier diodes (SBD) and power MOSFETs, for industrial and automotive applications. At the same time, the long-term reliability of these devices is a hot topic that should be addressed since there is limited field data to analyze. Some SiC providers have begun qualifying SiC devices to stringent industrial and automotive (AEC-Q101) standards, and others have even gone beyond the qualification standards requirements to also provide data for harsh ruggedness tests. This qualification and testing strategy, combined with the use of specific design rules for achieving high Avalanche ruggedness, are critical in order for SiC devices to sustain their fast adoption rates in mission- and safety-critical applications. Rapid Market Growth The growth in market share for SiC devices is expected to accelerate in the coming years, with the main driver being the electrification in the transportation sector. SiC dies will be an essential building block in modules for applications such as on-board chargers and powertrain traction systems. Thanks to the high critical electric field for avalanche breakdown, high-voltage SiC devices have a much smaller footprint than their silicon counterparts and can operate at higher switching frequencies. SiC’s thermal properties are also very attractive, with an excellent heat dissipation and the ability to operate at elevated temperatures. In practice, the maximum operating temperature is typically 175°C and rarely exceeds 200°C, the main limitation being the assembly process (soldering metal, package material). SiC devices are inherently more efficient than silicon ones, and the number of individual dies in a module can be drastically reduced by switching to SiC dies. As SiC devices move from niche to mainstream markets, the main challenges associated with the ramp-up to high volume manufacturing are being overcome. To ease this transition, fabrication plants are setting up SiC lines sharing tools with pre-existing silicon lines. This arrangement allows the cost to be lowered for the SiC dies as the overhead would be shared with Si. Recent constraints on wafer availability are becoming less of an issue with significant capacity increases by wafer vendors. Continuous improvements in 4H-SiC substrate and epitaxy growth lead to high-quality 6-inch wafers with a low density of crystal defects. The high quality of the wafers translates into high yield for SiC devices at electrical parameters tests. It is important to remember, though, that that there is limited reliability data from the field for these devices since they have only been commercially available for a few years. Also, the qualification of SiC devices has been significantly more arduous than that of silicon devices, with its own set of challenges. The electric field in reverse bias condition is close to one order of magnitude higher in SiC devices. Without proper design rules, this high electric field could easily damage the gate oxide. The density of traps near the gate oxide interface is also much higher for SiC. As a result, instabilities might arise during burn-in tests as traps get electrically charged. A persistent focus on long-term reliability improvement has yielded reassuring results, with recent reports of devices qualified to stringent industrial and automotive (AEC-Q101) standards. The talk would focus on reliability and ruggedness of SiC devices and what Microchip is doing to ensure its readiness for high volume automotive applications.
14:30 - 15:15
1200 V - 20 mOhm SiC MOSFET, Zuverlässigkeit und Performance für den Massenmarkt Martin Warnke, ON Semiconductor  
Die Vorteile und Stärken von Leistungehalbleitern auf basis von Siliciumcarbid (SiC) wurden über die letzten Jahre ausführlich und detailiert in eine viel Zahl von Vorträgen und Publikationen besprochen, die tatsächliche Akzeptanz für den Einsatz dieser Bauelemente findet jedoch noch immer mit vorsicht statt. Während SiC Dioden schon weit verbreitet eingesetzt werden, ist der Einsatz von SiC MOSFETs noch immer mit vielen Zuverlässigkeitsfragen verbunden. Tatsächlich ergibt eine kurze Marktstudie das viele Hersteller SiC MOSFETs unter 35 mOhm nicht anbieten, was hand in hand geht mit der Komplexität „large die“ SiC MOSFETs zu designen und zu qualifizieren. ON Semiconductor presentiert hier seinen neuen 20 mOhm (bei 100 A) 1200 V SiC MOSFET, welches in drei unterschielichen Packages, und in einer Vielzahl von Modulen zum Einsatz kommt. Dieses Bauelement erfühlt AEC-Q101 und ist einer der ersten hochstrom SiC MOSFETs für den Industriellen und Automobilen Einsatz. Wir presentieren Leistungs und Zuverlässigkeits Daten, sowie die Tücken welche mit der Qualifizierung von großen SiC MOSFET Bauelementen einhergehen.
15:15 - 15:45
Kaffeepause in der Ausstellung  
15:45 - 16:15
Application of GaN Devices with GaNdalf Edwin Kluter, Future Electronics
16:15 - 17:00
Verifiziertes dynamisches Simulationsmodell für GaN-HEMT-Bauelemente Achim Endruschat, Fraunhofer IISB; Holger Gerstner, Fraunhofer IISB  
NEU: In the first part of the presentation, the method of implementing a behavioral simulation model for a GaN-HEMT is presented. The model is purely based on own measurement data. Investigations regarding the static characterization showed that commercially available measurement setups are not suitable for a proper characterization. The design of an own static measurement test bench (Output Characteristics) is then discussed. In the dynamic range the model is verified using a double pulse measurement test bench. In the second part of the presentation the modeling of this double pulse test bench is shown from the 3D CAD model to the equivalent electrical circuit. Another focus is the determination of the parasitic switch capacitances. Together with the extracted inductances, the interaction between the switch and the electrical environment is explained. As a result, the verified switch model provides an important contribution to the application-oriented system simulation. With this approach, statements about the later system behavior can be made even before the first construction of a prototype.

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